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PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 28.Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53APPENDIX A.HARDWARE INTERFACE EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Figure43.Connection to Microcontroller, Without Glue Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . .54Figure 44.Connection to Microcontroller, With Glue Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55Figure 45.Building Storage Modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..55RELATED DOCUMENTATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Table 29.Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
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SUMMARY DESCRIPTION
The NAND Flash 528 Byte/ 264 Word Page is afamily of non-volatile Flash memories that usesthe Single Level Cell (SLC) NAND cell technology.It is referred to as the Small Page family. The de-vices range from 128Mbits to 1Gbit and operatewith either a 1.8V or 3V voltage supply. The size ofa Page is either 528 Bytes (512 + 16 spare) or 264Words (256 + 8 spare) depending on whether thedevice has a x8 or x16 bus width.
The address lines are multiplexed with the Data In-put/Output signals on a multiplexed x8 or x16 In-put/Output bus. This interface reduces the pincount and makes it possible to migrate to otherdensities without changing the footprint.
Each block can be programmed and erased over100,000 cycles. To extend the lifetime of NANDFlash devices it is strongly recommended to imple-ment an Error Correction Code (ECC). A WriteProtect pin is available to give a hardware protec-tion against program and erase operations.
The devices feature an open-drain Ready/Busyoutput that can be used to identify if the Program/Erase/Read (P/E/R) Controller is currently active.The use of an open-drain output allows the Ready/Busy pins from several memories to be connectedto a single pull-up resistor.
A Copy Back command is available to optimize themanagement of defective blocks. When a PageProgram operation fails, the data can be pro-grammed in another page without having to re-send the data to be programmed.
The devices are available in the following packag-es:■TSOP48 12 x 20mm for all products■USOP48 12 x 17 x 0.65mm for 128Mb, 256Mb
and 512Mb products■VFBGA55 (8 x 10 x 1mm, 6 x 8 ball array,
0.8mm pitch) for 128Mb and 256Mb products■TFBGA55 (8 x 10 x 1.2mm, 6 x 8 ball array,
0.8mm pitch) for 512Mb Dual Die product■VFBGA63 (9 x 11 x 1mm, 6 x 8 ball array,
0.8mm pitch) for the 512Mb product■TFBGA63 (9 x 11 x 1.2mm, 6 x 8 ball array,
0.8mm pitch) for the 1Gb Dual Die productTwo options are available for the NAND Flashfamily:
Chip Enable Don’t Care, which allows code to bedirectly downloaded by a microcontroller, as ChipEnable transitions during the latency time do notstop the read operation.
A Serial Number, which allows each device to beuniquely identified. The Serial Number options issubject to an NDA (Non Disclosure Agreement)and so not described in the datasheet. For moredetails of this option contact your nearest ST Salesoffice.
For information on how to order these options referto Table 28.,Ordering Information Scheme. De-vices are shipped from the factory with Block 0 al-ways valid and the memory content bits, in validblocks, erased to ’1’.
See Table 2.,Product Description, for all the de-vices available in the family.
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Table 2. Product Description
Timings
Reference
Part Number
Density
Bus Width
Page Size
BlockSize
Memory Array
Operating Voltage1.7 to 1.95V
32 Pages x 1024 Blocks
2.7 to 3.6V1.7 to 1.95V2.7 to 3.6V1.7 to 1.95V
32 Pages x 2048 Blocks
2.7 to 3.6V1.7to 1.95V2.7 to 3.6V1.7to 1.95V
32 Pages x 4096 Blocks
2.7 to 3.6V1.7 to 1.95V2.7 to 3.6V1.7to 1.95V
32 Pages x 4096 Blocks
2.7 to 3.6V1.7 to 1.95V2.7 to 3.6V1.7 to 1.95V
32 Pages x 8192 Blocks
2.7 to 3.6V1.7 to 1.95V2.7 to 3.6V
Random Sequential Access AccessMaxMin12µs12µs12µs12µs12µs12µs12µs12µs12µs12µs12µs12µs15µs12µs15µs12µs15µs12µs15µs12µs
60ns50ns60ns50ns60ns50ns60ns50ns60ns50ns60ns50ns60ns50ns60ns50ns60ns50ns60ns50ns
Page