See Figure 26. and Table 21. for details of the tim-ings requirements.Write Protect
Write Protect bus operations are used to protectthe memory against program or erase operations.When the Write Protect signal is Low the devicewill not accept program or erase operations and sothe contents of the memory array cannot be al-tered. The Write Protect signal is not latched byWrite Enable to ensure protection even duringpower-up.Standby
When Chip Enable is High the memory entersStandby mode, the device is deselected, outputsare disabled and power consumption is reduced.
Note:1.Only for x16 devices.
IH when issuing a program or erase command.
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Table 6. Address Insertion, x8 Devices
Bus Cycle
1st2nd3rd4th(4)
I/O7A7A16A24VIL
I/O6A6A15A23VIL
I/O5A5A14A22VIL
I/O4A4A13A21VIL
I/O3A3A12A20VIL
I/O2A2A11A19VIL
I/O1A1A10A18A26
I/O0A0A9A17A25
Note:1.A8 is set Low or High by the 00h or 01h Command, see Pointer Operations section.
2.Any additional address input cycles will be ignored.
3.The 4th cycle is only required for 512Mb and 1Gb devices.
Table 7. Address Insertion, x16 Devices
Bus Cycle1st2nd3rd4th(4)
Note:1.
2.3.4.
I/O8-I/O15XXXX
I/O7A7A16A24VIL
I/O6A6A15A23VIL
I/O5A5A14A22VIL
I/O4A4A13A21VIL
I/O3A3A12A20VIL
I/O2A2A11A19VIL
I/O1A1A10A18A26
I/O0A0A9A17A25
A8 is Don’t Care in x16 devices.
Any additional address input cycles will be ignored.The 01h Command is not used in x16 devices.
The 4th cycle is only required for 512Mb and 1Gb devices.
Table 8. Address Definitions
AddressA0 - A7A9 - A26A9 - A13A14 - A26
A8
DefinitionColumn AddressPage AddressAddress in BlockBlock Address
A8 is set Low or High by the 00h or 01h Command, and is
Don’t Care in x16 devices
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A
COMMAND SET
All bus write operations to the device are interpret-ed by the Command Interface. The Commandsare input on I/O0-I/O7 and are latched on the risingedge of Write Enable when the Command LatchEnable signal is high. Device operations are se-lected by writing specific commands to the Com-Table 9. Commands
Command
Read ARead BRead C
Read Electronic SignatureRead Status RegisterPage ProgramCopy Back ProgramBlock EraseReset
Bus Write Operations(1)
1st CYCLE
00h01h(2)50h90h70h80h00h60hFFh
2nd CYCLE
-----10h8AhD0h-3rd CYCLE
------10h--YesYes
Command accepted
during busy
mand Register. The two-step commandsequences for program and erase operations areimposed to maximize data security.
The Commands are summarized in Table9.,Commands.
Note:1.The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or input/output data are not shown.
2.Any undefined command sequence will be ignored by the device.
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