ProgramTypical200µs200µs200µs200µs200µs200µs200µs200µs200µs200µs200µs200µs200µs200µs200µs200µs200µs200µs200µs200µs
2ms
TSOP48TFBGA63
2ms
TSOP48USOP48VFBGA63
2ms
TFBGA55
2ms
TSOP48USOP48VFBGA55
2ms
TSOP48USOP48VFBGA55
Block EraseTypical
Package
NAND128R3A
NAND128-A
NAND128W3ANAND128R4ANAND128W4ANAND256R3A
NAND256-A
NAND256W3ANAND256R4ANAND256W4ANAND512R3A
NAND512-A(1)
NAND512W3ANAND512R4ANAND512W4ANAND512R3A
NAND512-A
NAND512W3ANAND512R4ANAND512W4ANAND01GR3A
NAND01G-A
NAND01GW3ANAND01GR4ANAND01GW4A
1Gbit512Mbit512Mbit256Mbit128Mbit
x8x16x8x16x8x16x8x16x8x16
512+16 16K+512 BytesBytes256+8 Words
8K+256 Words
512+16 16K+512 BytesBytes256+8 Words
8K+256 Words
512+16 16K+512 BytesBytes256+8 Words
8K+256 Words
512+16 16K+512 BytesBytes256+8 Words
8K+256 Words
512+16 16K+512 BytesBytes256+8 Words
8K+256 Words
Note:1.Dual Die device.
Table 3. Signal Names
I/O8-15
Data Input/Outputs for x16 devicesData Input/Outputs, Address Inputs, or Command Inputs for x8 and x16 devices
Address Latch EnableCommand Latch EnableChip EnableRead Enable
Ready/Busy (open-drain output)Write EnableWrite ProtectSupply VoltageGround
Not Connected InternallyDo Not Use
I/O0-7ALCLVDDVSSNCDU
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 4. TSOP48 and USOP48 Connections,
Figure 5. TSOP48 and USOP48 Connections,
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A
MEMORY ARRAY ORGANIZATION
The memory array is made up of NAND structureswhere 16 cells are connected in series.
The memory array is organized in blocks whereeach block contains 32 pages. The array is splitinto two areas, the main area and the spare area.The main area of the array is used to store datawhereas the spare area is typically used to storeError correction Codes, software flags or BadBlock identification.
In x8 devices the pages are split into a main areawith two half pages of 256 Bytes each and a sparearea of 16 Bytes. In the x16 devices the pages aresplit into a 256 Word main area and an 8 Wordspare area. Refer to Figure 10.,Memory Array Or-ganization.Bad Blocks
The NAND Flash 528 Byte/ 264 Word Page devic-es may contain Bad Blocks, that is blocks that con-tain one or more invalid bits whose reliability is notguaranteed. Additional Bad Blocks may developduring the lifetime of the device. The Bad Block Information is written prior to ship-ping (refer to Bad Block Management section formore details).
Table 4. shows the minimum number of validblocks in each device. The values shown includeboth the Bad Blocks that are present when the de-vice is shipped and the Bad Blocks that could de-velop later on.
These blocks need to be managed using BadBlocks Management, Block Replacement or ErrorCorrection Codes (refer to SOFTWARE ALGO-RITHMS section).Table 4. Valid Blocks
Density of Device
1Gbit512Mbits256Mbits128Mbits
Min8032401620081004
Max8192409620481024
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A
SIGNAL DESCRIPTIONS
See Figure 2.,Logic Diagram, and Table3.,Signal Names, for a brief overview of the sig-nals connected to this device.
Inputs/Outputs (I/O0-I/O7).Input/Outputs 0 to 7are used to input the selected address, output thedata during a Read operation or input a commandor data during a Write operation. The inputs arelatched on the rising edge of Write Enable. I/O0-I/O7 are left floating when the device is deselectedor the outputs are disabled.
Inputs/Outputs (I/O8-I/O15).Input/Outputs 8 to15 are only available in x16 devices. They areused to output the data during a Read operation orinput data during a Write operation. Command andAddress Inputs only require I/O0 to I/O7.
The inputs are latched on the rising edge of WriteEnable. I/O8-I/O15 are left floating when the de-vice is deselected or the outputs are disabled.Address Latch Enable (AL).The Address LatchEnable activates the latching of the Address inputsin the Command Interface. When AL is high, theinputs are latched on the rising edge of Write En-able.
Command Latch Enable (CL).The CommandLatch Enable activates the latching of the Com-mand inputs in the Command Interface. When CLis high, the inputs are latched on the rising edge ofWrite Enable.
The Chip Enable input acti-vates the memory control logic, input buffers, de-coders and sense amplifiers. When Chip Enable islow, VIL, the device is selected.