HYS64D128020GU-8-A中文资料

2020-05-03 18:06

HYS64/72D64000/128020GU-7/8-AUnbufferedDDR-ISDRAM-Modules

2.5V184-pinUnbufferedDDR-ISDRAMModules512MByte&1024MByteModulesPC1600,PC2100&PC2700

Preliminarydatasheetrev.0.81

?184-pinUnbuffered8-ByteDual-In-Line

DDR-ISDRAMnon-parityandECC-ModulesforPCandServermainmemoryapplications?Onebank64Mx64,64Mx72andtwobank128Mx64,128M×72organization?JEDECstandardDoubleDataRateSynchronousDRAMs(DDR-ISDRAM)Single+2.5V(±0.2V)powersupply?Builtwith512MbitDDR-ISDRAMsorganizedas64Mbx8in66-LeadTSOPIIpackage?ProgrammableCASLatency,BurstLength,andWrapSequence(Sequential&Interleave)?Performance:

-6

ComponentSpeedGradeModuleSpeedGrade

fCKfCK

?AutoRefresh(CBR)andSelfRefresh?AllinputsandoutputsSSTL_2compatible?SerialPresenceDetectwithE2PROM?JedecstandardMO-206formfactor:133.35mm×31.75mm×4.00mmmax.?Jedecstandardreferencelayout?Goldplatedcontacts

-7PC2100143133

-8PC1600125100

Unit

DDR333BDDR266ADDR200PC2700166133

MHzMHz

ClockFrequency(max.)@CL=2.5ClockFrequency(max.)@CL=2

TheHYS64/72D64000GUandHYS64/72D128020GUareindustrystandard184-pin8-byteDualin-lineMemoryModules(DIMMs)organizedas64M×64and128M×64fornon-parityand64Mx72and128Mx72forECCmainmemoryapplications.Thememoryarrayisdesignedwith512MbitDoubleDataRateSynchronousDRAMs.AvarietyofdecouplingcapacitorsaremountedonthePCboard.TheDIMMsfeatureserialpresencedetectbasedonaserialE2PROMdeviceusingthe2-pinI2Cprotocol.Thefirst128bytesareprogrammedwithconfigurationdataandthesecond128bytesareavailabletothecustomer.

INFINEONTechnologies12002-09-10(rev.0.81)

HYS64/72D64000/128x20GU-7/8-AUnbufferedDDR-ISDRAM-ModulesOrderingInformation

Type

PC2700(CL=2.5):HYS64D128320GU-6-AHYS72D128320GU-6-APC2100(CL=2):HYS64D64000GU-7-AHYS72D64000GU-7-AHYS64D128020GU-7-AHYS72D128020GU-7-APC1600(CL=2):HYS64D64000GU-8-AHYS72D64000GU-8-AHYS64D128020GU-8-AHYS72D128020GU-8-ANote:

PC1600-20220-A1PC1600-20220-A1PC1600-20220-B1PC1600-20220-B1

onebank512MBDIMMonebank512MBECC-DIMMtwobanks1024MBDIMMtwobanks1024MBECC-DIMM

512MBit512Mbit512MBit512MBit

PC2100-20330-A1PC2100-20330-A1PC2100-20330-B1PC2100-20330-B1

onebank512MBDIMMonebank512MBECC-DIMMtwobanks1024MBDIMMtwobanks1024MBECC-DIMM

512MBit512Mbit512MBit512MBit

PC2700-25330-B1PC2700-25330-B1

twobanks1024MBDIMMtwobanks1024MBECC-DIMM

512MBit512MBit

ComplianceCode

Description

SDRAMTechnology

Allpartnumbersendwithaplacecode,designatingthesilicon-dierevision.Referenceinformationavailableonrequest.Example:HYS72D64000GU-8-A,indicatingRev.AdiesareusedfortheSDRAMcomponents.

TheComplianceCodeisprintedonthemodulelabelsanddescribesthespeedsortfe.“PC2100”,thelatencies(f.e.“20330”meansCASlatency=2,trcdlatency=3andtrplatency=3)andtheRawCardusedforthismodule.

INFINEONTechnologies22002-09-10(rev.0.81)

HYS64/72D64000/128020GU-7/8-AUnbufferedDDR-ISDRAM-ModulesPinDefinitionsandFunctions

A0-A12BA0,BA1DQ0-DQ63CB0-CB7RASCASWECKE0-CKE1DQS0-DQS8CLK0-CLK2,CLK0-CLK2DM0-DM8DQS9-DQS17

AddressInputsBankSelectsDataInput/Output

CheckBits(x72organizationonly)RowAddressStrobeColumnAddressStrobeRead/WriteInputClockEnable

SDRAMlowdatastrobesSDRAMclock(positivelines)SDRAMclock(negativelines)SDRAMlowdatamask/highdatastrobes

S0,S1VDDVSSVDDQVDDIDVREFVDDSPDSCLSDASA0-SA2NC

ChipSelectsPower(+2.5V)Ground

I/ODriverpowersupplyVDDIndentificationflagI/Oreferencesupply

SerialEEPROMpowersupplySerialbusclockSerialbusdatalineslaveaddressselectnoconnect

note:S1andCKE1areusedontwobankmodulesonly

AddressFormat

Density512MB512MB

Organization64Mx6464Mx72

MemoryBanks1122

SDRAMs64Mx864Mx864Mx864Mx8

#of

SDRAMs891618

#ofrow/bank/columnsbits13/2/1113/2/1113/2/1113/2/11

Refresh8k8k8k8k

Period64ms64ms64ms64ms

Interval7.8μs7.8μs7.8μs7.8μs

1024MB128M×641024MB128M×72

INFINEONTechnologies32002-09-10(rev.0.81)

HYS64/72D64000/128x20GU-7/8-AUnbufferedDDR-ISDRAM-ModulesPinConfiguration

PIN#1234567891011121314151617181920212223242526272829303132333435363738394041424344454647FrontsideSymbolVREFDQ0VSSDQ1DQS0DQ2VDDDQ3NCNCVSSDQ8DQ9DQS1VDDQCLK1CLK1VSSDQ10DQ11CKE0VDDQDQ16DQ17DQS2VSSA9DQ18A7VDDQDQ19A5DQ24VSSDQ25DQS3A4VDDDQ26DQ27A2VSSA1NC/CB0NC/CB1VDDNC/DQS8FrontsidePIN#Symbol484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192A0NC/CB2VSSNC/CB3BA1KEYDQ32VDDQDQ33DQS4DQ34VSSBA0DQ35DQ40VDDQWEDQ41CASVSSDQS5DQ42DQ43VDDNCDQ48DQ49VSSCLK2CLK2VDDQDQS6DQ50DQ51VSSVDDIDDQ56DQ57VDDDQS7DQ58DQ59VSSNCSDASCLBacksidePIN#Symbol93949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139VSSDQ4DQ5VDDQDM0/DQS9DQ6DQ7VSSNCNCNCVDDQDQ12DQ13DM1/DQS10VDDDQ14DQ15CKE1VDDQNC(BA2)DQ20NC/A12VSSDQ21A11DM2/DQS11VDDDQ22A8DQ23VSSA6DQ28DQ29VDDQDM3/DQS12A3DQ30VSSDQ31NC/CB4NC/CB5VDDQCK0CK0VSSBacksidePIN#Symbol140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184NC/DM8/DQS17A10NC/CB6VDDQNC/CB7KEYVSSDQ36DQ37VDDDM4/DQS13DQ38DQ39VSSDQ44RASDQ45VDDQS0S1DM5/DQS14VSSDQ46DQ47NCVDDQDQ52DQ53NC(A13)VDDDM6/DQS15DQ54DQ55VDDQNCDQ60DQ61VSSDM7/DQS16DQ62DQ63VDDQSA0SA1SA2VDDSPDNote:Pins44,45,47,49,51,134,135,140and144areNC(“no-connects”)onx64organisednon-ECCmodules.INFINEONTechnologies42002-09-10(rev.0.81)

HYS64/72D64000/128020GU-7/8-AUnbufferedDDR-ISDRAM-ModulesDQS0DM0/DQS9DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7S0DQS4DM4/DQS13CSD0DQSDQ32DQ33DQ34DQ35DQ36DQ37DQ38DQ39DMI/O7I/O6I/O1I/O0I/O5I/O4I/O3I/O2CSD4DQSDMI/O7I/O6I/O1I/O0I/O5I/O4I/O3I/O2DQS1DM1/DQS10DQ8DQ9DQ10DQ11DQ12DQ13DQ14DQ15DMI/O7I/O6I/O1I/O0I/O5I/O4I/O3I/O2CSD1DQSDQS5DM5/DQS14DQ40DQ41DQ42DQ43DQ44DQ45DQ46DQ47DMI/O7I/O6I/O1I/O0I/O5I/O4I/O3I/O2CSD5DQSDQS2DM2/DQS11DQ16DQ17DQ18DQ19DQ20DQ21DQ22DQ23DMI/O7I/O6I/O1I/O0I/O5I/O4I/O3I/O2CSD2DQSDQS6DM6/DQS15DQ48DQ49DQ50DQ51DQ52DQ53DQ54DQ55DMI/O7I/O6I/O1I/O0I/O5I/O4I/O3I/O2CSD6DQSDQS3DM3/DQS12DQ24DQ25DQ26DQ27DQ28DQ29DQ30DQ31DMI/O7I/O6I/O1I/O0I/O5I/O4I/O3I/O2CSD3DQSDQS7DM7/DQS16DQ56DQ57DQ58DQ59DQ60DQ61DQ62DQ63DMI/O7I/O6I/O1I/O0I/O5I/O4I/O3I/O2CSD7DQS*ClockWiringSerialPDSDASCLA0SA0BA0-BA1A0-A11,A12VDD,VDDQVREFVSSVDDIDBA0,BA1:SDRAMsD0-D7A0-A11,A12:SDRAMsD0-D7RASD0-D7D0-D7D0-D7CASCKE0WERAS:SDRAMsD0-D7CAS:SDRAMsD0-D7CKE:SDRAMsD0-D7WE:SDRAMsD0-D7A1SA1A2SA2ClockInput*CK0/CK0*CK1/CK1*CK2/CK2SDRAMs2SDRAMs3SDRAMs3SDRAMs*WireperClockLoadingTable/WiringDiagramsNotes:1.DQ-to-I/Owiringisshownasrecom-mendedbutmaybechanged.2.DQ/DQS/DM/CKE/Srelationshipsmustbemaintainedasshown.3.DQ,DQS,DM/DQSresistors:22Ohms.4.VDDIDstrapconnections(formemorydeviceVDD,VDDQ):STRAPOUT(OPEN):VDD=VDDQBlockDiagram:OneBank64Mx64DDR-ISDRAMDIMMModuleHYS64D64000GUusingx8organizedSDRAMsINFINEONTechnologies

5

2002-09-10(rev.0.81)


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