HYS64/72D64000/128x20GU-7/8-AUnbufferedDDR-ISDRAM-ModulesS1S0DQS0DM0/DQS9DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7DMI/O7I/O6I/O1I/O0I/O5I/O4I/O3I/O2CSD0DQSDMI/O0I/O1I/O6I/O7I/O2I/O3I/O4I/O5CSDQSD8DQS4DM4/DQS13DQ32DQ33DQ34DQ35DQ36DQ37DQ38DQ39DMI/O7I/O6I/O1I/O0I/O5I/O4I/O3I/O2CSD4DQSDMI/O0I/O1I/O6I/O7I/O2I/O3I/O4I/O5CSD12DQSDQS1DM1/DQS10DQ8DQ9DQ10DQ11DQ12DQ13DQ14DQ15DMI/O7I/O6I/O1I/O0I/O5I/O4I/O3I/O2CSDQSD1DMI/O0I/O1I/O6I/O7I/O2I/O3I/O4I/O5CSDQSD9DQS5DM5/DQS14DQ40DQ41DQ42DQ43DQ44DQ45DQ46DQ47DMI/O7I/O6I/O1I/O0I/O5I/O4I/O3I/O2CSD5DQSDMI/O0I/O1I/O6I/O7I/O2I/O3I/O4I/O5CSD13DQSDQS2DM2/DQS11DQ16DQ17DQ18DQ19DQ20DQ21DQ22DQ23DMI/O7I/O6I/O1I/O0I/O5I/O4I/O3I/O2CSD2DQSDMI/O0I/O1I/O6I/O7I/O2I/O3I/O4I/O5CSD10DQSDQS6DM6/DQS15DQ48DQ49DQ50DQ51DQ52DQ53DQ54DQ55DMI/O7I/O6I/O1I/O0I/O5I/O4I/O3I/O2CSD6DQSDMI/O0I/O1I/O6I/O7I/O2I/O3I/O4I/O5CSD14DQSDQS3DM3/DQS12DQ24DQ25DQ26DQ27DQ28DQ29DQ30DQ31DMI/O7I/O6I/O1I/O0I/O5I/O4I/O3I/O2CSD3DQSDMI/O0I/O1I/O6I/O7I/O2I/O3I/O4I/O5CSD11DQSDQS7DM7/DQS16DQ56DQ57DQ58DQ59DQ60DQ61DQ62DQ63DMI/O7I/O6I/O1I/O0I/O5I/O4I/O3I/O2CSD7DQSDMI/O0I/O1I/O6I/O7I/O2I/O3I/O4I/O5CSDQSD15*ClockWiringBA0,BA1A0-A12VDD,VDDQVREFVSSVDDIDBA0,BA1:SDRAMsD0,D15A0-A12:SDRAMsD0-D15SDAD0-D15D0-D15SA0D0-D15SA1SA2SCLA0A1A2SerialPDClockInput*CK0/CK0*CK1/CK1*CK2/CK2SDRAMs4SDRAMs6SDRAMs6SDRAMs*WireperClockLoadingTable/WiringDiagramsCKE1RASCASCKE0WECKE:SDRAMsD8-D15RAS:SDRAMsD0-D15CAS:SDRAMsD0-D15CKE:SDRAMsD0-D7WE:SDRAMsD0-D15Notes:1.DQ-to-I/Owiringisshownasrecom-mendedbutmaybechanged.2.DQ/DQS/DM/CKE/Srelationshipsmustbemaintainedasshown.3.DQ,DQS,DM/DQSresistors:22Ohms.4.VDDIDstrapconnections(formemorydeviceVDD,VDDQ):STRAPOUT(OPEN):VDD=VDDQBlockDiagram:TwoBank128Mx64DDR-ISDRAMDIMMModulesHYS64D128020GUusingx8OrganizedSDRAMs
INFINEONTechnologies62002-09-10(rev.0.81)
HYS64/72D64000/128020GU-7/8-AUnbufferedDDR-ISDRAM-ModulesDQS0DM0/DQS9DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7S0DQS4DM4/DQS13CSD0DQSDQ32DQ33DQ34DQ35DQ36DQ37DQ38DQ39DMI/O7I/O6I/O1I/O0I/O5I/O4I/O3I/O2CSD4DQSDMI/O7I/O6I/O1I/O0I/O5I/O4I/O3I/O2DQS1DM1/DQS10DQ8DQ9DQ10DQ11DQ12DQ13DQ14DQ15DMI/O7I/O6I/O1I/O0I/O5I/O4I/O3I/O2CSDQSD1DQS5DM5/DQS14DQ40DQ41DQ42DQ43DQ44DQ45DQ46DQ47DMI/O7I/O6I/O1I/O0I/O5I/O4I/O3I/O2CSD5DQSDQS2DM2/DQS11DQ16DQ17DQ18DQ19DQ20DQ21DQ22DQ23DMI/O7I/O6I/O1I/O0I/O5I/O4I/O3I/O2CSD2DQSDQS6DM6/DQS15DQ48DQ49DQ50DQ51DQ52DQ53DQ54DQ55DMI/O7I/O6I/O1I/O0I/O5I/O4I/O3I/O2CSD6DQSDQS3DM3/DQS12DQ24DQ25DQ26DQ27DQ28DQ29DQ30DQ31DMI/O7I/O6I/O1I/O0I/O5I/O4I/O3I/O2CSD3DQSDQS7DM7/DQS16DQ56DQ57DQ58DQ59DQ60DQ61DQ62DQ63DMI/O7I/O6I/O1I/O0I/O5I/O4I/O3I/O2CSD7DQSDQS8DM8/DQS17CB0CB1CB2CB3CB4CB5CB6CB7BA0,BA1A0-A11,A12VDD,VDDQVREFVSSVDDIDDMI/O7I/O6I/O1I/O0I/O5I/O4I/O3I/O2CSD8SCLA0SA0A1SA1A2SA2DQSSerialPDSDABA0,BA1:SDRAMsD0-D8A0-A11,A12:SDRAMsD0-D8RASD0-D8D0-D8D0-D8CASCKE0WERAS:SDRAMsD0-D8CAS:SDRAMsD0-D8CKE:SDRAMsD0-D8WE:SDRAMsD0-D8*ClockWiringClockInput*CK0/CK0*CK1/CK1*CK2/CK2SDRAMs3SDRAMs3SDRAMs3SDRAMs*WireperClockLoadingTable/WiringDiagramsNotes:1.DQ-to-I/Owiringisshownasrecom-mendedbutmaybechanged.2.DQ/DQS/DM/CKE/Srelationshipsmustbemaintainedasshown.3.DQ,DQS,DM/DQSresistors:22Ohms.4.VDDIDstrapconnections(formemorydeviceVDD,VDDQ):STRAPOUT(OPEN):VDD=VDDQBlockDiagram:OneBank64Mx72DDR-ISDRAMDIMMModuleHYS72D64000GUusingx8organizedSDRAMsINFINEONTechnologies
7
2002-09-10(rev.0.81)
HYS64/72D64000/128x20GU-7/8-AUnbufferedDDR-ISDRAM-ModulesS1S0DQS0DM0/DQS9DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7DMI/O7I/O6I/O1I/O0I/O5I/O4I/O3I/O2CSD0DQSDMI/O0I/O1I/O6I/O7I/O2I/O3I/O4I/O5CSDQSD9DQS4DM4/DQS13DQ32DQ33DQ34DQ35DQ36DQ37DQ38DQ39DMI/O7I/O6I/O1I/O0I/O5I/O4I/O3I/O2CSD4DQSDMI/O0I/O1I/O6I/O7I/O2I/O3I/O4I/O5CSD13DQSDQS1DM1/DQS10DQ8DQ9DQ10DQ11DQ12DQ13DQ14DQ15DMI/O7I/O6I/O1I/O0I/O5I/O4I/O3I/O2CSD1DQSDMI/O0I/O1I/O6I/O7I/O2I/O3I/O4I/O5CSDQSD10DQS5DM5/DQS14DQ40DQ41DQ42DQ43DQ44DQ45DQ46DQ47DMI/O7I/O6I/O1I/O0I/O5I/O4I/O3I/O2CSD5DQSDMI/O0I/O1I/O6I/O7I/O2I/O3I/O4I/O5CSD14DQSDQS2DM2/DQS11DQ16DQ17DQ18DQ19DQ20DQ21DQ22DQ23DMI/O7I/O6I/O1I/O0I/O5I/O4I/O3I/O2CSD2DQSDMI/O0I/O1I/O6I/O7I/O2I/O3I/O4I/O5CSD11DQSDQS6DM6/DQS15DQ48DQ49DQ50DQ51DQ52DQ53DQ54DQ55DMI/O7I/O6I/O1I/O0I/O5I/O4I/O3I/O2CSD6DQSDMI/O0I/O1I/O6I/O7I/O2I/O3I/O4I/O5CSD15DQSDQS3DM3/DQS12DQ24DQ25DQ26DQ27DQ28DQ29DQ30DQ31DMI/O7I/O6I/O1I/O0I/O5I/O4I/O3I/O2CSD3DQSDMI/O0I/O1I/O6I/O7I/O2I/O3I/O4I/O5CSD12DQSDQS7DM7/DQS16DQ56DQ57DQ58DQ59DQ60DQ61DQ62DQ63DMI/O7I/O6I/O1I/O0I/O5I/O4I/O3I/O2CSDQSD7DMI/O0I/O1I/O6I/O7I/O2I/O3I/O4I/O5CSDQSD16DQS8DM8/DQS17CB0CB1CB2CB3CB4CB5CB6CB7DMI/O7I/O6I/O1I/O0I/O5I/O4I/O3I/O2CSD8DQSDMI/O7I/O6I/O1I/O0I/O5I/O4I/O3I/O2CSD17DQS*ClockWiringBA0,BA1A0-A12BA0,BA1:SDRAMsD0-D17A0-A12:SDRAMsD0-D17SDAVDD,VDDQVREFVSSVDDIDD0-D17D0-D17D0-D17SCLA0SA0A1SA1A2SA2SerialPDClockInput*CK0/CK0*CK1/CK1*CK2/CK2SDRAMs6SDRAMs6SDRAMs6SDRAMs*WireperClockLoadingTable/WiringDiagramsCKE1RASCASCKE0WECKE:SDRAMsD9-D17RAS:SDRAMsD0-D17CAS:SDRAMsD0-D17CKE:SDRAMsD0-D8WE:SDRAMsD0-D17Notes:1.DQ-to-I/Owiringisshownasrecom-mendedbutmaybechanged.2.DQ/DQS/DM/CKE/Srelationshipsmustbemaintainedasshown.3.DQ,DQS,DM/DQSresistors:22Ohms.4.VDDIDstrapconnections(formemorydeviceVDD,VDDQ):STRAPOUT(OPEN):VDD=VDDQBlockDiagram:TwoBank128Mx72DDR-ISDRAMDIMMModulesHYS72D128020GUusingx8OrganizedSDRAMsINFINEONTechnologies
8
2002-09-10(rev.0.81)
HYS64/72D64000/128020GU-7/8-AUnbufferedDDR-ISDRAM-ModulesClockNetWiring6DRAMLoads4DRAMLoadsDRAM1DRAM1DRAM2CKDIMMConnectorCKR=120DRAM3DIMMConnectorDRAM4DRAM5R=120DRAM2Cap.Cap.DRAM5DRAM6DRAM6DRAM13DRAMLoadsDRAM12DRAMLoadsCap.Cap.R=120DIMMConnectorCap.DRAM3DIMMConnectorR=120Cap.Cap.DRAM5DRAM5Cap.Cap.AbsoluteMaximumRatingsParameter
Input/OutputvoltagerelativetoVSSPowersupplyvoltageonVDD/VDDQtoVSSStoragetemperaturerange
Powerdissipation(perSDRAMcomponent)Dataoutcurrent(shortcircuit)
Symbol
min.
LimitValues
max.3.63.6+150150
VV
o
Unit
VIN,VOUTTSTGPDIOS
–0.5-55––
VDD,VDDQ–0.5
C
WmA
Permanentdevicedamagemayoccurif“AbsoluteMaximumRatings”areexceeded.Functionaloperationshouldberestrictedtorecommendedoperationconditions.
Exposuretohigherthanrecommendedvoltageforextendedperiodsoftimeaffectdevicereliability
INFINEONTechnologies92002-09-10(rev.0.81)
HYS64/72D64000/128x20GU-7/8-AUnbufferedDDR-ISDRAM-ModulesSupplyVoltageLevels
Parameter
Symbol
min.
DeviceSupplyVoltageOutputSupplyVoltageInputReferenceVoltageTerminationVoltageEEPROMsupplyvoltage
1)2)
LimitValuesnom.2.52.50.5xVDDQVREF2.5
max.2.72.70.51xVDDQVREF+0.043.6
UnitNotes
VDDVDDQVREFVTTVDDSPD
2.32.30.49xVDDQVREF–0.042.3
VVVVV
–
1)2)3)
3)
Underallconditions,VDDQmustbelessthanorequaltoVDD.
PeaktopeakACnoiseonVREFmaynotexceed±2%VREF(DC).VREFisalsoexpectedtotracknoisevariationsinVDDQ.
VTTofthetransmittingdevicemusttrackVREFofthereceivingdevice.
DCOperatingConditions(SSTL_2Inputs)
(VDDQ=2.5V,TA=70°C,VoltageReferencedtoVSS)
Parameter
Symbol
min.
DCInputLogicHighDCInputLogicLowInputLeakageCurrentOutputLeakageCurrent
1)
LimitValues
max.VDDQ+0.3VREF–0.1555
UnitNotes
1)
VIH(DC)VIL(DC)IILIOL
VREF+0.15–0.30–5–5
VV
–
2)2)
μAμA
2)
TherelationshipbetweentheVDDQofthedrivingdeviceandtheVREFofthereceivingdeviceiswhatdeterminesnoisemargins.However,inthecaseofVIH(max)(inputoverdrive),itistheVDDQofthereceivingdevicethatisreferenced.InthecasewhereadeviceisimplementedsuchthatitsupportsSSTL_2inputsbuthasnoSSTL_2outputs(suchasatranslator),andthereforenoVDDQsupplyvoltageconnection,inputsmusttolerateinputoverdriveto3.0V(HighcornerVDDQ+300mV).
Foranypinundertestinputof0V≤VIN≤VDDQ+0.3V.ValuesareshownperDDR-SDRAMcomponent.
INFINEONTechnologies102002-09-10(rev.0.81)