HYS64/72D64000/128020GU-7/8-AUnbufferedDDR-ISDRAM-ModulesOperating,StandbyandRefreshCurrents(PC1600)
512MBx641bank-8512MBx721bank-81GBx642bank-81GBx722bank-8NotesSymbolParameter/ConditionUnitMAXIDD0OperatingCurrent:onebank;active/precharge;tRC=tRCMIN;tCK=tCKMIN;DQ,DM,andDQSinputschangingonceperclockcycle;addressandcontrolinputschangingonceeverytwoclockcyclesOperatingCurrent:onebank;active/read/precharge;Burst=4;Refertothefollowingpagefordetailedtestconditions.PrechargePower-DownStandbyCurrent:allbanksidle;power-downmode;CKE<=VILMAX;tCK=tCKMINPrechargeFloatingStandbyCurrent:/CS>=VIHMIN,allbanksidle;CKE>=VIHMIN;tCK=tCKMIN,addressandothercontrolinputschangingonceperclockcycle,VIN=VREFforDQ,DQSandDM.PrechargeQuietStandbyCurrent:/CS>=VIHMIN,allbanksidle;CKE>=VIHMIN;tCK=tCKMIN,addressandothercontrolinputsstableat>=VIHMINor<=VILMAX;VIN=VREFforDQ,DQSandDM.ActivePower-DownStandbyCurrent:onebankactive;power-downmode;CKE<=VILMAX;tCK=tCKMIN;VIN=VREFforDQ,DQSandDM.1280MAX1440MAX1680MAX1890mA41IDD11360153017601980mA1,3IDD2P96108192216mA2IDD2F320360640720mA2IDD2Q200225400450mA2IDD3P128144256288mA2ActiveStandbyCurrent:onebankactive;active/precharge;CS>=VIHMIN;CKE>=VIHMIN;tRC=tRASMAX;tCK=tCKMIN;DQ,DM,andIDD3NDQSinputschangingtwiceperclockcycle;addressandcontrolinputschangingonceperclockcycleOperatingCurrent:onebankactive;Burst=2;reads;continuousburst;addressandcontrolinputschangingonceperclockcycle;50%ofdataIDD4Routputschangingoneveryclockedge;CL=2forDDR200,andDDR266A,CL=3forDDR333;tCK=tCKMIN;IOUT=0mAOperatingCurrent:onebankactive;Burst=2;writes;continuousburst;addressandcontrolinputschangingonceperclockcycle;50%ofdataIDD4Woutputschangingoneveryclockedge;CL=2forDDR200,andDDR266A,CL=3forDDR333;tCK=tCKMINIDD5IDD6IDD7Auto-RefreshCurrent:tRC=tRFCMIN,distributedrefreshSelf-RefreshCurrent:CKE<=0.2V;externalclockon;tCK=tCKMINOperatingCurrent:fourbank;fourbankinterleavingwithBL=4;Refertothefollowingpagefordetailedtestconditions.400450800900mA21320148517201935mA1,31280144016801890mA12320402800261045315027208032003060903600mAmAmA11,31.ThemoduleIDDvaluesarecalculatedfromthecomponentIDDdatasheetvaluesas:n*IDDx[component]forsinglebankmodules(n:numberofcomponentspermodulebank)n*IDDx[component]+n*IDD3N[component]fortwobankmodules(n:numberofcomponentspermodulebank)2.ThemoduleIDDvaluesarecalculatedfromthecomponentIDDdatasheetvaluesas:n*IDDx[component]forsinglebankmodules(n:numberofcomponentspermodulebank)2*n*IDDx[component]fortwobankmodules(n:numberofcomponentspermodulebank)3.DQI/O(IDDQ)currentsarenotincludedintocalculations:moduleIDDvalueswillbemeasureddifferentlydependingonloadconditions4.Testconditionformaximumvalues:VDD=2.7V,Ta=10°CINFINEONTechnologies112002-09-10(rev.0.81)
HYS64/72D64000/128x20GU-7/8-AUnbufferedDDR-ISDRAM-ModulesOperating,StandbyandRefreshCurrents(PC2100andPC2700)
512MB512MB1GBx64x64x721bank1bank2bank-6-7-71GB1GB1GBx72x64x722bank2bank2bank-6-7-7Notes4mA1SymbolParameter/ConditionUnitMAXIDD0OperatingCurrent:onebank;active/precharge;tRC=tRCMIN;tCK=tCKMIN;DQ,DM,andDQSinputschangingonceperclockcycle;addressandcontrolinputschangingonceeverytwoclockcyclesOperatingCurrent:onebank;active/read/precharge;Burst=4;Refertothefollowingpagefordetailedtestconditions.PrechargePower-DownStandbyCurrent:allbanksidle;power-downmode;CKE<=VILMAX;tCK=tCKMINPrechargeFloatingStandbyCurrent:/CS>=VIHMIN,allbanksidle;CKE>=VIHMIN;tCK=tCKMIN,addressandothercontrolinputschangingonceperclockcycle,VIN=VREFforDQ,DQSandDM.PrechargeQuietStandbyCurrent:/CS>=VIHMIN,allbanksidle;CKE>=VIHMIN;tCK=tCKMIN,addressandothercontrolinputsstableat>=VIHMINor<=VILMAX;VIN=VREFforDQ,DQSandDM.ActivePower-DownStandbyCurrent:onebankactive;power-downmode;CKE<=VILMAX;tCK=tCKMIN;VIN=VREFforDQ,DQSandDM.1360MAX1530MAX2200MAX2475MAX1920MAX2160IDD1144016202320261020002250mA1,3IDD2P112126288324224252mA2IDD2F4004509601080800900mA2IDD2Q224252640720448504mA2IDD3P144162368414288324mA2ActiveStandbyCurrent:onebankactive;active/precharge;CS>=VIHMIN;CKE>=VIHMIN;tRC=tRASMAX;tCK=tCKMIN;DQ,DM,andIDD3NDQSinputschangingtwiceperclockcycle;addressandcontrolinputschangingonceperclockcycleOperatingCurrent:onebankactive;Burst=2;reads;continuousburst;addressandcontrolinputschangingonceperclockcycle;50%ofdataIDD4Routputschangingoneveryclockedge;CL=2forDDR200,andDDR266A,CL=3forDDR333;tCK=tCKMIN;IOUT=0mAOperatingCurrent:onebankactive;Burst=2;writes;continuousburst;addressandcontrolinputschangingonceperclockcycle;50%ofdataIDD4Woutputschangingoneveryclockedge;CL=2forDDR200,andDDR266A,CL=3forDDR333;tCK=tCKMINIDD5IDD6IDD7Auto-RefreshCurrent:tRC=tRFCMIN,distributedrefreshSelf-RefreshCurrent:CKE<=0.2V;externalclockon;tCK=tCKMINOperatingCurrent:fourbank;fourbankinterleavingwithBL=4;Refertothefollowingpagefordetailedtestconditions.5606301200135011201260mA2160018002560288021602430mA1,3156017552480279021202385mA1248040304027904534203280803840369090432030408036003420904050mAmAmA11,31.ThemoduleIDDvaluesarecalculatedfromthecomponentIDDdatasheetvaluesas:n*IDDx[component]forsinglebankmodules(n:numberofcomponentspermodulebank)n*IDDx[component]+n*IDD3N[component]fortwobankmodules(n:numberofcomponentspermodulebank)2.ThemoduleIDDvaluesarecalculatedfromthecomponentIDDdatasheetvaluesas:n*IDDx[component]forsinglebankmodules(n:numberofcomponentspermodulebank)2*n*IDDx[component]fortwobankmodules(n:numberofcomponentspermodulebank)3.DQI/O(IDDQ)currentsarenotincludedintocalculations:moduleIDDvalueswillbemeasureddifferentlydependingonloadconditions4.Testconditionformaximumvalues:VDD=2.7V,Ta=10°CINFINEONTechnologies122002-09-10(rev.0.81)
HYS64/72D64000/128020GU-7/8-AUnbufferedDDR-ISDRAM-ModulesElectricalCharacteristics&ACTimingforDDR-Icomponents(forreferenceonly)
(0°C≤ TA≤ 70 °C; VDDQ=2.5V± 0.2V;VDD=2.5V± 0.2V)
DDR333-6MintACtDQSCKtCHtCLtHPtCKtCKtDHtDStIPWtDIPWtHZtLZtDQSStDQSQtQHStQHtDQSL,HtDSStDSHtMRDtWPREStWPSTtWPREtISDQoutputaccesstimefromCK/CKDQSoutputaccesstimefromCK/CKCKhigh-levelwidthCKlow-levelwidthClockHalfPeriodClockcycletimeCL=2.5CL=2.0?0.7?0.7SymbolParameterDDR266A-7Min?0.75?0.75DDR200-8Min?0.8?0.8UnitnsnstCKtCKnsnsnsnsnsnsnsNotes1-41-41-41-41-41-41-41-41-41,101-4,111-4,51-4,51-41-41-41-41-41-41-41-41-4,71-4,61-4Max+0.7+0.7Max+0.75+0.75Max+0.8+0.80.450.450.550.550.450.450.550.550.450.450.550.55min(tCL,tCH)67.50.450.452.21.75?0.7?0.7+0.7+0.7min(tCL,tCH)77.50.50.52.21.75?0.75?0.75+0.75+0.75min(tCL,tCH)8100.60.62.52?0.8?0.8+0.8+0.81212––12121212DQandDMinputholdtimeDQandDMinputsetuptimeControlandAddr.inputpulsewidth(eachinput)DQandDMinputpulsewidth(eachinput)Data-outhigh-impedencetimefromCK/CKData-outlow-impedencetimefromCK/CKWritecommandto1stDQSlatchingtransitionDQS-DQskew(forDQS&associatedDQsignals)DataholdskewfactorDataOutputholdtimefromDQSDQSinputlow(high)pulsewidth(writecycle)DQSfallingedgetoCKsetuptime(writecycle)DQSfallingedgeholdtimefromCK(writecycle)ModeregistersetcommandcycletimeWritepreamblesetuptimeWritepostambleWritepreambleAddressandcontrolinputsetuptimeAddressandcontrolinputholdtimeReadpreambleReadpostambleActivetoPrechargecommandActivetoActive/Auto-refreshcommandperiodfastslewrateslowslewratefastslewrateslowslewratensnstCKnsnsnstCKtCKtCKnsns0.751.25+0.40.751.25+0.50.751.25+0.6+0.55tHP-tQHS0.350.20.21200.400.250.75–tHP-tQHS0.350.20.21400.600.400.250.91.0+0.75tHP-tQHS0.350.20.21600.600.400.251.11.11.11.11.10.60120,000+1.00.60tCKtCKnsnsnsnstIHtRPREtRPSTtRAStRC0.750.91.02-4,10,110.90.4042600.90.4045650.90.4050701.10.60120,000tCKtCKnsns1-41-41-41-4INFINEONTechnologies132002-09-10(rev.0.81)
HYS64/72D64000/128020GU-7/8-AUnbufferedDDR-ISDRAM-ModulesElectricalCharacteristics&ACTimingforDDR-Icomponents(forreferenceonly)
(0°C≤ TA≤ 70 °C; VDDQ=2.5V± 0.2V;VDD=2.5V± 0.2V)
DDR333-6MintRFCtRCDtRPtRRDtWRtDALtWTRtXSNRtXSRDtREFIAuto-refreshtoActive/Auto-refreshcommandperiodActivetoReadorWritedelayPrechargecommandperiodActivebankAtoActivebankBcommandWriterecoverytimeAutoprechargewriterecovery+prechargetimeInternalwritetoreadcommanddelayExitself-refreshtonon-readcommandExitself-refreshtoreadcommandAveragePeriodicRefreshInterval512Mbitbased7218181215(twr/tck)+(trp/tck)1752007.8MaxDDR266A-7Min7520201515(twr/tck)+(trp/tck)1752007.81802007.8MaxDDR200-8Min8020201515MaxnsnsnsnsnstCKtCKnstCKμsSymbolParameterUnitNotes1-41-41-41-41-41-4,91-41-41-41-4,81.Inputslewrate>=1V/nsforDDR266and=1V/nsforDDR200.2.TheCK/CKinputreferencelevel(fortimingreferencetoCK/CK)isthepointatwhichCKandCKcross:theinputreferencelevelforsignalsotherthanCK/CK,isVREF.CK/CKslewrateare>=1.0V/ns.3.InputsarenotrecognizedasvaliduntilVREFstabilizes.4.TheOutputtimingreferencelevel,asmeasuredatthetimingreferencepointindicatedinACCharacteristics(Note3)isVTT.5.tHZandtLZtransitionsoccurinthesameaccesstimewindowsasvaliddatatransitions.Theseparametersarenotreferredtoaspecificvoltagelevel,butspecifywhenthedeviceisnolongerdriving(HZ),orbeginsdriving(LZ).6.Themaximumlimitforthisparameterisnotadevicelimit.Thedeviceoperateswithagreatervalueforthisparameter,butsystemperformance(busturnaround)degradesaccordingly.7.ThespecificrequirementisthatDQSbevalid(HIGH,LOW,orsomepointonavalidtransition)onorbeforethisCKedge.Avalidtransitionisdefinedasmonotonicandmeetingtheinputslewratespecificationsofthedevice.Whennowriteswerepreviouslyinprogressonthebus,DQSwillbetransitioningfromHi-ZtologicLOW.Ifapreviouswritewasinprogress,DQScouldbeHIGH,LOW,ortransitioningfromHIGHtoLOWatthistime,dependingontDQSS.8.AmaximumofeightAutorefreshcommandscanbepostedtoanygivenDDRSDRAMdevice.9.Foreachoftheterms,ifnotalreadyaninteger,roundtothenexthighestinteger.tCKisequaltotheactualsystemclockcycletime.10.Theseparametersguaranteedevicetiming,buttheyarenotnecessarilytestedoneachdevice11.Fastslewrate>=1.0V/ns,slowslewrate>=0.5V/nsand<1V/nsforcommand/addressandCK&CKslewrate>1.0V/ns,measuredbetweenVOH(ac)andVOL(ac)INFINEONTechnologies142002-09-10(rev.0.81)
HYS64/72D64000/128020GU-7/8-AUnbufferedDDR-ISDRAM-ModulesSPDCodesforPC1600Modules“-8”
Byte#Description512MBx641bank-8HEX8008070D0B01400004808000820800010E040C010220C0A0800000503C503280B0B06060004650303CA00000E8C1INFINEON512MBx721bank-8HEX8008070D0B01480004808002820808010E040C010220C0A0800000503C503280B0B06060004650303CA00000FAC1INFINEON1GBx642bank-8HEX8008070D0B02400004808000820800010E040C010220C0A0800000503C503280B0B06060004650303CA00000E9C1INFINEON1GBx722bank-8HEX8008070D0B02480004808002820808010E040C010220C0A0800000503C503280B0B06060004650303CA00000FBC1INFINEON0123456789101112131415161718192021222324252627282930313233343536-40414243444546-6162636465-717273-9091-9293-9495-9899-127128-255NumberofSPDBytesTotalBytesinSerialPDMemoryTypeNumberofRowAddressesNumberofColumnAddressesNumberofDIMMBanksModuleDataWidthModuleDataWidth(cont’d)ModuleInterfaceLevelsSDRAMCycleTimeatCL=2.5AccessTimefromClockatCL=2.5DIMMConfigRefreshRate/TypeSDRAMWidth,PrimaryErrorCheckingSDRAMDataWidthMinimumClockDelayforBack-to-BackRandomColumnAddressBurstLengthSupportedNumberofSDRAMBanksSupportedCASLatenciesCSLatenciesWELatenciesSDRAMDIMMModuleAttributesSDRAMDeviceAttributes:GeneralMin.ClockCycleTimeatCASLatency=2AccessTimefromClockforCL=2MinimumClockCycleTimeatCL=1.5AccessTimefromClockatCL=1.5MinimumRowPrechargeTimeMinimumRowAct.toRowAct.DelaytRRDMinimumRAStoCASDelaytRCDMinimumRASPulseWidthtRASModuleBankDensity(perbank)Addr.andCommandSetupTimeAddr.andCommandHoldTimeDataInputSetupTimeDataInputHoldTimeSupersetInformationMinimumCoreCycleTimetRCMin.AutoRefreshCmdCycleTimetRFCMaximumClockCycleTimetckMax.DQS-DQSkewtDQSQX-FactortQHSSupersetInformationSPDRevisionChecksumforBytes0-62ManufacturersJEDECIDCodeManufacturerModuleAssemblyLocationModulePartNumberModuleRevisionCodeModuleManufacturingDateModuleSerialNumber–openforCustomeruse128256DDR-SDRAM13111/2x64/x720SSTL_2.58ns0.8nsnon-ECC/ECCSelf-Refresh,7.8msx8na/x8tccd=1CLK2,4&84CASlatency=2&2.5CSlatency=0Writelatency=1unbuffered–10.0ns0.8nsnotsupportednotsupported20ns15ns20ns50ns512MByte1.1ns1.1ns0.6ns0.6ns–70ns80ns12ns0.6ns1.0ns-Revision0.0––––––––––INFINEONTechnologies152002-09-10(rev.0.81)