第2-2讲 VHDL语言的基本结构
Out与Buffer的区别Entity test1 is port(a: in std_logic; b,c: out std_logic ); end test1; architecture a of test1 is begin b <= not(a); c <= b;--Error end a; Entity test2 is port(a: in std_logic; b : buffer std_logic; c: out std_logic ); end test2; architecture a of test2 is begin b <= not(a); c <= b; end a;