移位寄存器设计verilog
input reset,
output reg Synch_out);
wire Clr,Clr_in; reg q1,q2;
always @(posedge Asynch_in or negedge Clr) if(!Clr)
q1<=1'b0; else
q1<=1'b1;
always @(posedge clock or negedge Clr) if(!Clr)
q2<=1'b0; else
q2<=q1;
always @(posedge clock or negedge reset) if(!reset)
Synch_out<=1'b0; else
Synch_out<=q2;
and (Clr_in,!Asynch_in,Synch_out); or (Clr,Clr_in,reset);
endmodule
验证代码：
`timescale 1ns/1ps
module syn_b_test; reg Asynch_in; reg clock,reset; wire Synch_out;
always #50 clock=~clock;
initial begin
clock=1; reset=1;
Asynch_in=1; #30 reset=0;
#20 Asynch_in=0; #50 reset=1;
#50 Asynch_in=1;