eda课程设计,游戏机!vhdl语言,Quartus II 7.0
architecture fangdou_player2_body of fangdou_player2 is signal mp1,mp2:std_logic; begin
process(clk_100) begin
if(clk_100'event and clk_100='0') then mp2<=mp1;
mp1<=player2_b; end if; end process;
player2<=clk_100 and mp1 and (not mp2); end fangdou_player2_body;
c. 计数器
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity count is
port( clk_1:in std_logic; switch:in std_logic;
player1,player2:in std_logic;
sum1,sum2:out integer range 0 to 10
图6 计数器 );
end count;
architecture count_body of count is
signal p1,p2:integer range 0 to 10 ; begin
sum1<=p1; sum2<=p2;
process(player1,player2,switch,clk_1) begin
if(switch='1') then
if(clk_1='0') then --p1<=0; --p2<=0;
if(player1'event and player1='1')
then