eda课程设计,游戏机!vhdl语言,Quartus II 7.0
end if;
if(player2'event and player2='1') then
p2<=p2+1; end if; else
p1<=0; p2<=0; end if; else
p1<=0; p2<=0; end if; end process; end count_body;
d. 译码器
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
图7 译码器
entity devode is
port( clk_1:in std_logic; clk:in std_logic;
nixie_state1,nixie_state2:in std_logic_vector(1 downto 0); leds_state:in std_logic_vector(2 downto 0); nixie1:out std_logic_vector(6 downto 0); nixie2:out std_logic_vector(6 downto 0); leds:out std_logic_vector(6 downto 0) ); end devode;
architecture devode_body of devode is
signal tmp_leds:std_logic_vector(6 downto 0); signal tmp_nixie1:std_logic_vector(6 downto 0); signal tmp_nixie2:std_logic_vector(6 downto 0); signal tmp_nixiea:std_logic_vector(6 downto 0); signal tmp_nixieb:std_logic_vector(6 downto 0);
begin
leds<=tmp_leds;