Count<=0; else if(enable) begin if(!dnup) begin
if(Count==Ktop) Count<=0; else
Count<=Count+1; end else begin if(Count==0) Count<=Ktop; else
Count<=Count-1; end end end
//输出进位脉冲carry和借位脉冲borrow assign carry=enable&(!dnup)&(Count==Ktop); assign borrow=enable&dnup&(Count==0); endmodule
module idcounter(IDclock,reset,inc,dec,IDout);//脉冲增减模块 input IDclock,reset,inc,dec; output IDout; reg IDout;
reg inc_new,dec_new,inc_pulse,dec_pulse; reg delayed,advanced,Tff;
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always @(posedge IDclock) begin if(!inc) begin inc_new<=1; inc_pulse<=0; end else if (inc_pulse) begin inc_new<=0; inc_pulse<=0; end else if (inc&&inc_new) begin
inc_pulse<=1; inc_new<=0; end else begin
inc_pulse<=0; inc_new<=0; end end
always @(posedge IDclock) begin if(!dec) begin
dec_new<=1; dec_pulse<=0; end
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else if (dec_pulse) begin dec_new<=0; dec_pulse<=0; end
else if (dec&&dec_new) begin
dec_pulse<=1; dec_new<=0; end else begin
dec_pulse<=0; dec_new<=0; end end
always@(posedge IDclock) begin
if (reset)
begin Tff<=0; delayed<=1;advanced<=1; end else begin
if (inc_pulse)
begin advanced<=1;Tff<=!Tff; end else if(dec_pulse)
begin delayed<=1; Tff<=!Tff; end else if (Tff==0) begin
if(!advanced) Tff<=!Tff;
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else if(advanced)
begin Tff<=Tff; advanced<=0; end end else begin if (!delayed) Tff<=!Tff; else if(delayed)
begin Tff<=Tff;delayed<=0; end end end end
always @(IDclock or Tff) begin if (Tff) IDout=0; else begin
if(IDclock) IDout=0; else IDout=1; end end endmodule
module counter_N(clk, fin, reset, count_N);//利用clk对fin脉冲的测量并给出N值
input clk, fin, reset; output [14:0] count_N;
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reg [14:0] count_N; reg [15:0] cnt; reg cnt_en; reg load;
wire cnt_clr;
always @ (posedge fin )//fin上升沿到的时候，产生各种标志以便后面控制 begin if (reset) begin cnt_en=0; load=1; end else begin
cnt_en=~cnt_en; load=~cnt_en; end end
assign cnt_clr=~(~fin & load);
always @(posedge clk or negedge cnt_clr) begin
if (!cnt_clr) cnt=0; else if (cnt_en) begin
if (cnt==15531) cnt=0; else cnt=cnt+1; end
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end
always @ (posedge load) begin
count_N=cnt/2; //这里取fin周期的一半 end endmodule
4.N分频模块
module div_N(clkin,n,reset,clkout); //N分频模块 input clkin,reset; input [14:0] n; output clkout; reg clkout; integer count; always@(posedge clkin) if(reset) begin clkout<=0; count<=0; end else begin
if(count>=(n/2)-1)
begin clkout<=~clkout;count<=0;end else
count<=count+1; end endmodul
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