end
always @ (posedge load) begin
count_N=cnt/2; //这里取fin周期的一半 end endmodule
4.N分频模块
module div_N(clkin,n,reset,clkout); //N分频模块 input clkin,reset; input [14:0] n; output clkout; reg clkout; integer count; always@(posedge clkin) if(reset) begin clkout<=0; count<=0; end else begin
if(count>=(n/2)-1)
begin clkout<=~clkout;count<=0;end else
count<=count+1; end endmodul
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