ELSIF(ST='1' AND CNT<7) THEN
CNT<=CNT+1;
IF(DTEMP(11)='1')THEN
CRCVAR:=DTEMP(11 DOWNTO 6)XOR MULTI_COEF;
DTEMP<=CRCVAR(4 DOWNTO 0)& DTEMP(5 DOWNTO 0) & '0';
ELSE DTEMP<=DTEMP(10 DOWNTO 0) & '0';
END IF;
ELSIF(ST='1' AND CNT=7) THEN
DATACRCO<=SDATAM & DTEMP(11 DOWNTO 7); HSEND<='1'; CNT<=CNT+1;
ELSIF(ST='1' AND CNT=8) THEN
HSEND<='0'; ST<='0'; END IF; END IF;
END PROCESS; END COMM;
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四川理工学院本科毕业（设计）论文
附 录B
CRC校验查错模块
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY CRCREC IS
PORT( DATACRCI:IN STD_LOGIC_VECTOR(16 DOWNTO 0); CLK,HRECV: IN STD_LOGIC;
RDATA:OUT STD_LOGIC_VECTOR(11 DOWNTO 0); ERROR1,DATAFINI:OUT STD_LOGIC); END CRCREC;
ARCHITECTURE COMM OF CRCREC IS
CONSTANT MULTI_COEF:STD_LOGIC_VECTOR(5 DOWNTO 0) := \ SIGNAL RCNT:STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNAL RDTEMP:STD_LOGIC_VECTOR(11 DOWNTO 0); SIGNAL RDATACRC:STD_LOGIC_VECTOR(16 DOWNTO 0); SIGNAL RT:STD_LOGIC; BEGIN
PROCESS(CLK,HRECV)
VARIABLE RCRCVAR : STD_LOGIC_VECTOR(5 DOWNTO 0);
BEGIN
IF(CLK'EVENT AND CLK = '1')THEN
IF(RT='0'AND HRECV='1')THEN
RDTEMP<=DATACRCI(16 DOWNTO 5);
RDATACRC<=DATACRCI;
RCNT<=(OTHERS=>'0'); ERROR1<='0'; RT<='1';
ELSIF(RT='1'AND RCNT<7)THEN
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DATAFINI<='0'; RCNT<=RCNT+1;
RCRCVAR:=RDTEMP(11 DOWNTO 6)XOR MULTI_COEF; IF(RDTEMP(11)='1')THEN
RDTEMP<=RCRCVAR(4 DOWNTO 0)&RDTEMP(5 DOWNTO 0)& '0';
ELSE
RDTEMP<=RDTEMP(10 DOWNTO 0) & '0';
END IF;
ELSIF(RT='1' AND RCNT=7)THEN DATAFINI<='1';
RDATA<=RDATACRC(16 DOWNTO 5);RT<='0';
IF(RDATACRC(4 DOWNTO 0) /=RDTEMP(11 DOWNTO 7)) THEN ERROR1<='1';
END IF;
END IF;
END IF;
END PROCESS; END COMM;
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