乐山职业技术学院毕业设计
参考文献
[1]潘松，黄继业.EDA技术实用教程（第二版）.科学出版社,2007.9
[2] 徐守堂刘艳惠，李娜，孔旭梅.EDA技术教程.西北师范大学知行学院—计算机与电子信息科学系 [3]潭会生，张昌凡.EDA技术及应用.西安电子科技大学出版社,2001.9 [4]李洋. EDA技术使用教程.机械工业出版社,2002.3
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乐山职业技术学院毕业设计
附录
1、递增波形源程序
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY icrs IS
PORT(clk,reset: IN STD_LOGIC;
q: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END icrs;
ARCHITECTURE behave OF icrs IS
BEGIN
PROCESS(clk,reset)
VARIABLE tmp : STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN
IF reset='0' THEN
tmp:= \复位信号清零 ELSIF clk'EVENT AND clk='1' THEN IF tmp=\
tmp:=\递增到最大值清零 ELSE
tmp:=tmp+1;--递增运算 END IF; END IF; q<=tmp;
END PROCESS; END behave;
2、递减波形源程序 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY dcrs IS
PORT (clk,reset:IN STD_LOGIC;
q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END dcrs;
ARCHITECTURE behave OF dcrs IS BEGIN
PROCESS(clk,reset)
VARIABLE tmp:STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN
IF reset='0' THEN
tmp:=\复位信号置最大值
ELSIF clk'EVENT AND clk='1' THEN--检测时钟上升沿 IF tmp=\
tmp:=\递减到0置最大值 ELSE
tmp:=tmp-1;--递减运算
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乐山职业技术学院毕业设计
END IF; END IF; q<=tmp;
END PROCESS; END behave;
3、三角波形源程序 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY delta IS
PORT(clk,reset:IN STD_LOGIC;
q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); end delta;
ARCHITECTURE behave OF delta IS BEGIN
PROCESS(clk,reset) VARIABLE tmp:STD_LOGIC_VECTOR(7 DOWNTO 0); VARIABLE a:STD_LOGIC; BEGIN
IF reset='0' THEN
tmp:=\复位信号为0，置最小值
ELSIF clk'EVENT AND clk='1' THEN--检测时钟上升沿 IF a='0' THEN
IF tmp=\tmp:=\置最大值
a:='1';
ELSE --不是最大值时递增 tmp:=tmp+1;--递增运算 END IF;
ELSE
IF tmp =\tmp:=\置最小值 a:='0';
ELSE --a为1时，执行递减运算 tmp:=tmp-1;--递减运算 END IF; END IF; END IF; q<=tmp;
END PROCESS; END behave;
4、阶梯波形程序源程序
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ladder IS
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乐山职业技术学院毕业设计
PORT(clk,reset:IN STD_LOGIC;
q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ladder;
ARCHITECTURE behave OF ladder IS
BEGIN
PROCESS(clk,reset)
VARIABLE tmp: STD_LOGIC_VECTOR(7 DOWNTO 0); --定义内部变量 VARIABLE a: STD_LOGIC; BEGIN
IF reset='0' THEN
tmp:=\复位信号为0，置最小值
ELSIF clk'EVENT AND clk='1' THEN--检测时钟上升沿 IF a='0' THEN--判断a数值，计数。 IF tmp=\
tmp:=\计数到最大清零 a:='1'; ELSE
tmp:=tmp+16;--阶梯常数为16，可修改 a:='1'; END IF; ELSE
a:='0';--循环计数 END IF; END IF;
q<=tmp;
END PROCESS; END behave;
5、正弦波源程序 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY sin IS
PORT(clk,clr:IN STD_LOGIC;
d: OUT INTEGER RANGE 0 TO 255); END sin ;
ARCHITECTURE behave OF sin IS BEGIN
PROCESS(clk,clr)
VARIABLE tmp: INTEGER RANGE 0 TO 63; BEGIN IF clr='0'THEN d<=0;
ELSIF clk'EVENT AND clk='1'THEN IF tmp=63 THEN tmp:=0; ELSE
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乐山职业技术学院毕业设计
tmp:=tmp+1; END IF;
CASE tmp IS
WHEN 00=>d<=255;WHEN 01=>d<=254;WHEN 02=>d<=252; WHEN 03=>d<=249;WHEN 04=>d<=245;WHEN 05=>d<=239; WHEN 06=>d<=233;WHEN 07=>d<=225;WHEN 08=>d<=217; WHEN 09=>d<=207;WHEN 10=>d<=197;WHEN 11=>d<=186; WHEN 12=>d<=174;WHEN 13=>d<=162;WHEN 14=>d<=150; WHEN 15=>d<=137;WHEN 16=>d<=124;WHEN 17=>d<=112; WHEN 18=>d<=99; WHEN 19=>d<=87; WHEN 20=>d<=75; WHEN 21=>d<=64; WHEN 22=>d<=53; WHEN 23=>d<=43; WHEN 24=>d<=34; WHEN 25=>d<=26; WHEN 26=>d<=19; WHEN 27=>d<=13; WHEN 28=>d<=8; WHEN 29=>d<=4; WHEN 30=>d<=1; WHEN 31=>d<=0; WHEN 32=>d<=0; WHEN 33=>d<=1; WHEN 34=>d<=4; WHEN 35=>d<=8; WHEN 36=>d<=13; WHEN 37=>d<=19; WHEN 38=>d<=26; WHEN 39=>d<=34; WHEN 40=>d<=43; WHEN 41=>d<=53; WHEN 42=>d<=64; WHEN 43=>d<=75; WHEN 44=>d<=87; WHEN 45=>d<=99; WHEN 46=>d<=112;WHEN 47=>d<=124; WHEN 48=>d<=137;WHEN 49=>d<=150;WHEN 50=>d<=162; WHEN 51=>d<=174;WHEN 52=>d<=186;WHEN 53=>d<=197; WHEN 54=>d<=207;WHEN 55=>d<=217;WHEN 56=>d<=225; WHEN 57=>d<=233;WHEN 58=>d<=239;WHEN 59=>d<=245; WHEN 60=>d<=249;WHEN 61=>d<=252;WHEN 62=>d<=254; WHEN 63=>d<=255;
WHEN OTHERS=>NULL; END CASE; END IF; END PROCESS;
END behave; 6、方波源程序 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY square IS
PORT(clk,clr:IN STD_LOGIC; q:OUT INTEGER RANGE 0 TO 255); END square;
ARCHITECTURE behave OF square IS SIGNAL a:BIT; BEGIN
PROCESS(clk,clr)
VARIABLE cnt:INTEGER; --定义内部整数变量 BEGIN
IF clr='0' THEN
a<='0';
ELSIF clk'EVENT AND clk='1' THEN--检测时钟上升沿
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乐山职业技术学院毕业设计
IF cnt<63 THEN--计数64个点 cnt:=cnt+1;--计数
ELSE
cnt:=0; --当计数的值大于64时，清零。
a<=NOT a; --对内部a变量取反，a变化已启动进程END PROCESS; END IF; END IF; END PROCESS; PROCESS(clk,a) BEGIN
IF clk'EVENT AND clk='1' THEN IF a='1' THEN
q<=255; --a=1,输出一个波形周期内的高电平 ELSE
q<=0; --a=0,输出一个波形周期的低电平。 END IF; END IF; END PROCESS; END behave;
7、波形选择模块源程序
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ch61a IS
PORT(sel:IN STD_LOGIC_VECTOR(2 DOWNTO 0); d0,d1,d2,d3,d4,d5:IN STD_LOGIC_VECTOR(7 DOWNTO 0); q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ch61a;
ARCHITECTURE behave OF ch61a IS BEGIN
PROCESS(sel) BEGIN
CASE sel IS
WHEN\递增波形输出 WHEN\递减波形输出 WHEN\三角波形输出 WHEN\阶梯波形输出 WHEN\正弦波形输出 WHEN\方波输出 WHEN OTHERS=>NULL; END CASE; END PROCESS; END behave;
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