基于FPGA的数字频率计实验报告(能测占空比) - 图文(4)

2019-08-31 17:35

end if; end if;

------------------**p3_3--显示低位**--------------------------------

if(d1='0')then

dip6:=1;------小于X10000档的低四位不显示小数点---- if(dip5=1)then ge<=aa; shi<=bb; bai<=cc; qian<=dd;

dip6:=0;------X10000档的高位不显示小数点------- dip7:=1;------X10000档的低位千位显示小数点----- elsif(dip4=1)then ge<=0; shi<=aa; bai<=bb; qian<=cc;

elsif(dip3=1)then ge<=0; shi<=0; bai<=aa; qian<=bb;

elsif(dip2=1)then ge<=0; shi<=0; bai<=0; qian<=aa; else

ge<=0; shi<=0; bai<=0;

qian<=0; end if;

elsif(d1='1')then dip6:=0; dip7:=0;

end if;

end if;

--------------------**p3_4---占空比**-------------------------------

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if(clk_10m'event and clk_10m='1')then counter2:=counter2+1;

if(counter2=1000000)then---10mhz频率,计数到1000000为1s-- c:=zc;--------停止检测高电平并锁存高四位计数器值------ d:=zd; e:=ze;

f:=zf; end if; end if;

if(clkx='1')then--------测待测方波高电平------

if(clk_10m'event and clk_10m='1')then counter3:=counter3+1; za:=za+1; if(za=10)then za:=0; zb:=zb+1; if(zb=10)then zb:=0; zc:=zc+1; if(zc=10)then zc:=0; zd:=zd+1; if(zd=10)then zd:=0; ze:=ze+1;

if(ze=10)then ze:=0; zf:=zf+1;

if(zf=10)then zf:=0; end if; end if; end if; end if; end if; end if; end if; end if;

-------------------**p3_4--数码管显示部分**-------------------------

if(clk_1hz'event and clk_1hz='1')then-----1s显示一次频率-----

-------**小数点显示**------

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if(dip7=1)then

led4(7)<='1'; led3(7)<='1'; led2(7)<='1'; led1(7)<='0';

elsif(dip5=1 or dip6=1)then led4(7)<='1'; led3(7)<='1'; led2(7)<='1'; led1(7)<='1'; elsif(dip4=1)then led4(7)<='0'; led3(7)<='1'; led2(7)<='1'; led1(7)<='1'; elsif(dip3=1)then

led4(7)<='1'; led3(7)<='0'; led2(7)<='1'; led1(7)<='1'; elsif(dip2=1)then

led4(7)<='1'; led3(7)<='1'; led2(7)<='0'; led1(7)<='1'; elsif(dip1=1 )then

led4(7)<='1'; led3(7)<='1'; led2(7)<='1'; led1(7)<='0'; end if;

---------**显示数字**---------------- Case qian is

when 0=>led1(6 downto 0)<=\ when 1=>led1(6 downto 0)<=\ when 2=>led1(6 downto 0)<=\ when 3=>led1(6 downto 0)<=\ when 4=>led1(6 downto 0)<=\ when 5=>led1(6 downto 0)<=\ when 6=>led1(6 downto 0)<=\ when 7=>led1(6 downto 0)<=\ when 8=>led1(6 downto 0)<=\ when 9=>led1(6 downto 0)<=\

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when others=>led1(6 downto 0)<=\end case;

case bai is

when 0=>led2(6 downto 0)<=\when 1=>led2(6 downto 0)<=\when 2=>led2(6 downto 0)<=\when 3=>led2(6 downto 0)<=\when 4=>led2(6 downto 0)<=\when 5=>led2(6 downto 0)<=\when 6=>led2(6 downto 0)<=\when 7=>led2(6 downto 0)<=\when 8=>led2(6 downto 0)<=\when 9=>led2(6 downto 0)<=\

when others=>led2(6 downto 0)<=\end case;

case shi is

when 0=>led3(6 downto 0)<=\when 1=>led3(6 downto 0)<=\when 2=>led3(6 downto 0)<=\when 3=>led3(6 downto 0)<=\when 4=>led3(6 downto 0)<=\when 5=>led3(6 downto 0)<=\when 6=>led3(6 downto 0)<=\when 7=>led3(6 downto 0)<=\when 8=>led3(6 downto 0)<=\when 9=>led3(6 downto 0)<=\

when others=>led3(6 downto 0)<=\end case;

case ge is

when 0=>led4(6 downto 0)<=\when 1=>led4(6 downto 0)<=\when 2=>led4(6 downto 0)<=\when 3=>led4(6 downto 0)<=\when 4=>led4(6 downto 0)<=\when 5=>led4(6 downto 0)<=\when 6=>led4(6 downto 0)<=\when 7=>led4(6 downto 0)<=\when 8=>led4(6 downto 0)<=\when 9=>led4(6 downto 0)<=\

when others=>led4(6 downto 0)<=\end case;

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clr:=1;---------显示完后清零------ end if;

-----**计数器清零**----- if(clr=1)then

aa:=0; bb:=0; cc:=0; dd:=0; ee:=0; ff:=0; gg:=0; hh:=0;

za:=0; zb:=0; zc:=0; zd:=0; ze:=0; zf:=0;

dip1:=0; dip2:=0; dip3:=0; dip4:=0; dip5:=0;

temp2:=0; temp3:=0; temp4:=0; temp5:=0;

counter2:=0; counter3:=0;

clr:=0;------退出清零---

end if; end process p3;

--*************p4**数码管扫描******************************

p4 : process(clk) is

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variable counter4 :integer range 0 to 3:=0; begin

if(freq12k'event and freq12k='1') then counter4:=counter4+1; case counter4 is

when 0 => wei <= \ when 1 => wei <= \ when 2 => wei <= \ when 3 => wei <= \ when others => null; end case; end if;

end process p4;

end architecture abc;

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