° CLB: 50 high by 1 wide ° DSP48: 10 high by 1 wide ° Block RAM: 10 high by 1 wide
? Base Regions in UltraScale? FPGAs are: ° CLB: 60 high by 1 wide ° DSP48: 24 high by 1 wide ° Block RAM: 12 high by 1 wide ° I/O and Clocking: 52 I/O (one bank), plus related XiPhy, MMCM, and PLL resources ° Gigabit Transceivers: 4 high (one quad, plus related clocking resources)
一个实际的例子（ug947）
第三步：综合
导航到解压到文件夹，运行脚本，5个都通过后，会产生三个日志文件。 第四步：
第五步：建立floorplan
第六步：实现第一个配置 1.加载顶层约束
read_xdc Sources/xdc/top_io.xdc
此约束设置器件的管脚分配和顶层时序约束。XDC不能通过IDE环境访问到，不会以设计源文件的方式出现。
顶层XDC文件应该只包含关于静态设计的object。 2. 优化，布局布线。 opt_design place_design route_design
3.保存完整设计的checkpoint
write_checkpoint -force Implement/Config_shift_right_count_up/top_route_design.dcp 4.保存每个RM的checkpoint
write_checkpoint -force -cell inst_shift Checkpoint/shift_right_route_design.dcp write_checkpoint -force -cell inst_count Checkpoint/count_up_route_design.dcp
此时，你已经创建了一个完整实现的partial reconfiguration design,可以生成full and partial bitstreams.静态部分可以用于下一步的配置，为了隔离静态设计，需要把RM模块移除。
5.确保资源布线使能，放大一个带有partition pins的interconnect tile. 6.清除RM逻辑
update_design -cell inst_shift -black_box
update_design -cell inst_count -black_box 执行前后的变化是： 完全布线（绿色）减少了；
在Netlist视图中inst_shift和inst_count空了；
7.锁定当前的布局布线
lock_design -level routing
变成虚线了。
8.执行下面的指令保存只有静态的checkpoint
write_checkpoint -force Checkpoint/static_route_design.dcp 第七步：实现第二个配置
1.使用锁定的结果，读取后综合checkpoint
2.优化，布局布线
read_checkpoint -cell inst_shift Synth/shift_left/shift_synth.dcp
read_checkpoint -cell inst_count Synth/count_down/count_synth.dcp opt_design place_design route_design
实现完第二个配置的设计是虚实线结合的设计。虚线表示锁定的布线，实线表示最新的布线。 3.保存full design checkpoint.
write_checkpoint -force Implement/Config_shift_left_count_down/top_route_design.dcp report_utilization -file Implement/Config_shift_left_count_down/top_utilization.rpt
report_timing_summary -file Implement/Config_shift_left_count_down/top_timing_summary.rpt 4. 可选的一步
write_checkpoint -force -cell inst_shift Checkpoint/shift_left_route_design.dcp
write_checkpoint -force -cell inst_count Checkpoint/count_down_route_design.dcp 第八步：检查结果
1.在TCL控制台，发起下列指令
source hd_visual/pblock_inst_shift_AllTiles.tcl
highlight_objects -color blue [get_selected_objects]
2.在Device视图中，点击某处取消选中frames，然后发起下列命令：
source hd_visual/pblock_inst_count_AllTiles.tcl
highlight_objects -color yellow [get_selected_objects] 高亮的tiles代表要去生成partial的配置帧。 3.关闭当前工程 第九步：生成比特文件
1.运行pr_verify命令
pr_verify
Implement/Config_shift_right_count_up/top_route_design.dcp
Implement/Config_shift_left_count_down/top_route_design.dcp
产生比特文件
1. 将第一个配置读进memory
open_checkpoint Implement/Config_shift_right_count_up/top_route_design.dcp 2.产生full和partial比特文件。要注意产生的路径要区分开来。
write_bitstream -file Bitstreams/Config_RightUp.bit
close_project
3.为第二个配置产生full 和partial文件
open_checkpoint Implement/Config_shift_left_count_down/top_route_design.dcp write_bitstream -file Bitstreams/Config_LeftDown.bit
close_project
4.产生带黑箱的full文件，和空的partial文件。空的partial文件可以擦除原有的配置来减少功耗。
open_checkpoint Checkpoint/static_route_design.dcp update_design -cell inst_count -buffer_ports update_design -cell inst_shift -buffer_ports place_design route_design
write_checkpoint Checkpoint/Config_black_box.dcp write_bitstream -file Bitstreams/config_black_box.bit
close_project
基础的配置文件没有任何reconfig分区。update_design命令插入0常量。place_design和route_design命令确保他们的完全实现。
第10步：部分配置 1. 连接好下载线。
2. Flow>Open Hardware Manager 3. Open a new hardware target. 4. Program device. 注意full的时间。
Partially reconfigure the device. 1. Program device. 2. Program device. Description
What configuration modes work with partial reconfiguration?
Solution
Partial reconfiguration is supported through the following configuration interfaces: JTAG
The JTAG interface is dedicated. SelectMAP
If PERSIST is set and the mode is set to slave, the interface remains active. Load the partial reconfiguration bitstream as a typical flow.
If PERSIST is set and the mode is set to master, CCLK runs continuously. This makes controlling the data flow more involved. It is recommended that you use the ICAP interface instead of PERSIST in the master SelectMAP mode.
If PERSIST is not set, you can forward the data to ICAP. You can also use the STARTUP block to drive the CCLK out. See the ICAP section below for more information. Note that you must account for the clock and the data alignment. BPI
BPI supports master mode only. This results in the CCLK being driven and continuous address incrementation. It is recommended that you avoid using PERSIST and that you use the ICAP interface instead to forward the data through the BPI data port. SPI
SPI supports master mode only. This results in the CCLK being driven and no further read commands are issued after configuration. It is recommended that you avoid using PERSIST and that you use ICAP interface instead to forward the data through the BPI data port. ICAP