参考文献
[1] [2] [3] [4] [5] [6]
任文平，梁竹关.EDA技术与FPGA工程实例开发.北京:机械工业出版社，2013 潘松，黄继业，等.EDA技术实用教程[M]. 北京：科学出版社，2010.
冯建国，俞一鸣.FPGA现代数字系统设计[M].北京：清华大学出版社，2010. 焦素敏.EDA技术基础.北京：清华大学出版社，2009. 王穿新.FPGA设计基础.北京:高等教育出版社,2009. 王振红. VHDL数字电路设计与应用实践教程. 北京：机械工业出版社，2006.
16
附 录
1附顶层原理图
2分频
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity fenpin is
port (clk:in std_logic;
clk_1khz:out std_logic; clk_100hz:out std_logic; clk_10hz:out std_logic; clk_2hz:out std_logic; clk_1hz:out std_logic );
end entity fenpin;
architecture fen_n of fenpin is
signal cnter0:integer range 0 to 24999:=0; signal cnter1:integer range 0 to 4:=0; signal cnter2:integer range 0 to 4:=0; signal cnter3:integer range 0 to 4:=0; signal cnter4:integer range 0 to 4:=0; signal cnter5:integer range 0 to 24:=0;
17
signal
clk_1khztmp,clk_100hztmp,clk_10hztmp,clk_2hztmp,clk_1hztmp,clk_0_1hztmp:std_logic:='0'; begin
process(clk) is begin
if clk 'event and clk='1' then if cnter0=24999 then cnter0<=0;
clk_1khztmp<=not clk_1khztmp; else
cnter0<=cnter0+1; end if; end if; end process;
clk_1khz<=clk_1khztmp; process(clk_1khztmp) is begin
if clk_1khztmp 'event and clk_1khztmp='1' then if cnter1=4 then cnter1<=0;
clk_100hztmp<=not clk_100hztmp; else
cnter1<=cnter1+1; end if; end if; end process;
clk_100hz<=clk_100hztmp; process(clk_100hztmp) is begin
if clk_100hztmp 'event and clk_100hztmp='1' then if cnter2=4 then cnter2<=0;
clk_10hztmp<=not clk_10hztmp; else
cnter2<=cnter2+1; end if; end if; end process;
clk_10hz<=clk_10hztmp; process(clk_100hztmp) is begin
if clk_100hztmp 'event and clk_100hztmp='1' then if cnter5=24 then cnter5<=0;
18
clk_2hztmp<=not clk_2hztmp; else
cnter5<=cnter5+1; end if; end if; end process;
clk_2hz<=clk_2hztmp; process(clk_10hztmp) is begin
if clk_10hztmp 'event and clk_10hztmp='1' then if cnter3=4 then cnter3<=0;
clk_1hztmp<=not clk_1hztmp; else
cnter3<=cnter3+1; end if; end if; end process;
clk_1hz<=clk_1hztmp; end fen_n;
3消抖
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; entity xiaodou is
port( clk1:in std_logic; key:in std_logic;
key_out:OUT STD_LOGIC );
end entity xiaodou;
ARCHITECTURE behave OF xiaodou IS begin
PROCESS(CLK1,key)
VARIABLE COUNT1 :INTEGER RANGE 0 TO 99; BEGIN
IF key='0' THEN
IF clk1'event and clk1='1' THEN
IF COUNT1<99 THEN COUNT1:=COUNT1+1; ELSE COUNT1:=0; END IF;
19
IF COUNT1=98 THEN key_out<='0'; ELSE key_out<='1'; END IF; END IF;
ELSE COUNT1:=0; END IF;
END PROCESS ; END BEHAVE;
4显示
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; entity xianshi is
port(clk:in std_logic;
miaoge:in std_logic_vector(3 downto 0); miaoshi:in std_logic_vector(3 downto 0); fenge:in std_logic_vector(3 downto 0); fenshi:in std_logic_vector(3 downto 0); xiaoge:in std_logic_vector(3 downto 0); xiaoshi:in std_logic_vector(3 downto 0); zhou:in std_logic_vector(3 downto 0);
mb0:in std_logic_vector(3 downto 0); mb1:in std_logic_vector(3 downto 0); mb2:in std_logic_vector(3 downto 0); mb3:in std_logic_vector(3 downto 0); mb4:in std_logic_vector(3 downto 0); mb5:in std_logic_vector(3 downto 0); mb6:in std_logic_vector(3 downto 0);
amh:in std_logic_vector(3 downto 0); aml:in std_logic_vector(3 downto 0); afh:in std_logic_vector(3 downto 0); afl:in std_logic_vector(3 downto 0); ahh:in std_logic_vector(3 downto 0); ahl:in std_logic_vector(3 downto 0); key:in std_logic_vector(1 downto 0);
shanshuo:in std_logic_vector(1 downto 0);
Q:BUFFER STD_LOGIC_VECTOR(2 DOWNTO 0); DOUT: OUT STD_LOGIC_VECTOR(4 DOWNTO 0) );
end entity xianshi;
20