数电课程设计报告(5)

2019-09-02 14:10

ARCHITECTURE behave OF xianshi IS

signal QIN: INTEGER RANGE 6 DOWNTO 0; signal count: INTEGER RANGE 0 TO 999; begin

p1: process(clk) begin

if clk'event and clk='1' then IF QIN>6 THEN QIN<=0; ELSE

QIN<=QIN+1; END IF;

if count>999 then count<=0; else

count<=count+1; end if; END IF;

END PROCESS P1;

P2: PROCESS(QIN) BEGIN

if key=\ then CASE QIN IS

WHEN 0=>DOUT<='0'&mb0(3 DOWNTO 0);Q<=\ WHEN 1=>DOUT<='0'&mb1(3 DOWNTO 0);Q<=\ WHEN 2=>DOUT<='0'&mb2(3 DOWNTO 0);Q<=\ WHEN 3=>DOUT<='1'&mb3(3 DOWNTO 0);Q<=\ WHEN 4=>DOUT<='0'&mb4(3 DOWNTO 0);Q<=\ WHEN 5=>DOUT<='0'&mb5(3 DOWNTO 0);Q<=\ WHEN 6=>DOUT<=\ WHEN OTHERS=>NULL; END CASE;

elsif key=\

if shanshuo=\ if count<499 then CASE QIN IS

WHEN 0=>DOUT<='0'&MIAOGE(3 DOWNTO 0);Q<=\ WHEN 1=>DOUT<='0'&MIAOSHI(3 DOWNTO 0);Q<=\ WHEN 2=>DOUT<='1'&FENGE(3 downto 0);Q<=\ WHEN 3=>DOUT<='0'&FENSHI(3 DOWNTO 0);Q<=\

WHEN 4=>DOUT<='1'&XIAOGE(3 DOWNTO 0);Q<=\ WHEN 5=>DOUT<='0'&XIAOSHI(3 DOWNTO 0);Q<=\ WHEN 6=>DOUT<='1'&ZHOU(3 DOWNTO 0);Q<=\ WHEN OTHERS=>NULL; END CASE;

elsif count>499 then CASE QIN IS

WHEN 0=>DOUT<='0'&MIAOGE(3 DOWNTO 0);Q<=\ WHEN 1=>DOUT<='0'&MIAOSHI(3 DOWNTO 0);Q<=\ WHEN 2=>DOUT<=\

WHEN 3=>DOUT<='0'&FENSHI(3 DOWNTO 0);Q<=\ WHEN 4=>DOUT<='1'&XIAOGE(3 DOWNTO 0);Q<=\ WHEN 5=>DOUT<='0'&XIAOSHI(3 DOWNTO 0);Q<=\ WHEN 6=>DOUT<='1'&ZHOU(3 DOWNTO 0);Q<=\ WHEN OTHERS=>NULL; END CASE; end if;

elsif shanshuo=\ if count<499 then CASE QIN IS

WHEN 0=>DOUT<='0'&MIAOGE(3 DOWNTO 0);Q<=\ WHEN 1=>DOUT<='0'&MIAOSHI(3 DOWNTO 0);Q<=\ WHEN 2=>DOUT<='1'&FENGE(3 downto 0);Q<=\ WHEN 3=>DOUT<='0'&FENSHI(3 DOWNTO 0);Q<=\ WHEN 4=>DOUT<='1'&XIAOGE(3 DOWNTO 0);Q<=\ WHEN 5=>DOUT<='0'&XIAOSHI(3 DOWNTO 0);Q<=\ WHEN 6=>DOUT<='1'&ZHOU(3 DOWNTO 0);Q<=\ WHEN OTHERS=>NULL; END CASE;

elsif count>499 then CASE QIN IS

WHEN 0=>DOUT<='0'&MIAOGE(3 DOWNTO 0);Q<=\ WHEN 1=>DOUT<='0'&MIAOSHI(3 DOWNTO 0);Q<=\ WHEN 2=>DOUT<='1'&FENGE(3 downto 0);Q<=\ WHEN 3=>DOUT<='0'&FENSHI(3 DOWNTO 0);Q<=\ WHEN 4=>DOUT<=\

WHEN 5=>DOUT<='0'&XIAOSHI(3 DOWNTO 0);Q<=\ WHEN 6=>DOUT<='1'&ZHOU(3 DOWNTO 0);Q<=\ WHEN OTHERS=>NULL; END CASE; end if;

elsif shanshuo=\ then if count<499 then CASE QIN IS

elsif count>499 then CASE QIN IS

elsif shanshuo=\ then CASE QIN IS

else

CASE QIN IS

WHEN 0=>DOUT<='0'&aml(3 DOWNTO 0);Q<=\ WHEN 1=>DOUT<='0'&amh(3 DOWNTO 0);Q<=\ WHEN 2=>DOUT<='1'&afl(3 DOWNTO 0);Q<=\ WHEN 3=>DOUT<='0'&afh(3 DOWNTO 0);Q<=\ WHEN 4=>DOUT<=\ Q<=\ WHEN 5=>DOUT<=\ Q<=\

WHEN 6=>DOUT<=\ Q<=\ WHEN OTHERS=>NULL; END CASE; end if;

END PROCESS P2;

END behave;

5译码

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY yima IS PORT(

NUM :IN STD_LOGIC_VECTOR(4 DOWNTO 0); LED8:OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END;

ARCHITECTURE BEHA OF YIMA IS BEGIN

PROCESS(NUM) BEGIN

CASE NUM IS

WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\

WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\

WHEN\ WHEN\ WHEN\

when others=>LED8<=\ END CASE; END PROCESS; END;

6闹钟

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; entity naozhong is port(

clk1k:in std_logic; ma:in std_logic_vector(3 downto 0); mb:in std_logic_vector(3 downto 0); mc:in std_logic_vector(3 downto 0); md:in std_logic_vector(3 downto 0); na:in std_logic_vector(3 downto 0); nb:in std_logic_vector(3 downto 0); nc:in std_logic_vector(3 downto 0); nd:in std_logic_vector(3 downto 0); me:in std_logic_vector(3 downto 0); mf:in std_logic_vector(3 downto 0); clk2HZ:in std_logic; beep: out std_logic );

end entity naozhong;

ARCHITECTURE behave OF naozhong IS begin

process(ma) begin

if (mc=na and md=nb and me=nc and mf=nd and ma=\then

beep<=clk1k; end if;

共6页:

数电课程设计报告(5).doc 将本文的Word文档下载到电脑下载失败或者文档不完整，请联系客服人员解决！

下载这篇word文档