ENTITY counter IS PORT (
clk
: IN BIT;
up_down : IN BIT; ld : IN BIT;
D : IN INTEGER RANGE 0 TO 255; Q
: OUT INTEGER RANGE 0 TO 255 );
END counter;
ARCHITECTURE a OF counter IS BEGIN PROCESS (clk) VARIABLE cnt
BEGIN
IF (up_down = '1') THEN
direction := 1; direction := -1; ELSE END IF;
IF (clk'EVENT AND clk = '1') THEN
IF ld = '0' THEN
cnt := d;
cnt := cnt + direction; ELSE END IF;
: INTEGER RANGE 0 TO 255;
VARIABLE direction : INTEGER;
END IF; Q <= cnt;
END PROCESS; END a;
[解] 这部分VHDL程序结构体是行为描述，实现了可逆计数器的逻辑功能。 3.23 分析下面的VHDL程序，说明电路的功能并画出逻辑电路图。 LIBRARY ieee；
USE ieee.std_logic_1164.all； ENTITY alarm IS
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PORT( smoke, door, water：IN STA_LOGIC； alarm_en ：IN STA_LOGIC；
fire_alarm, burg_alarm, water_alarm：OUT STA_LOGIC )； END alarm ；
ARCHITECTURE alarm_arc OF alarm IS SIGNAL i1, i2, i3：BIT；
COMPONENT nor2 PORT（x，y：in Bit；z：OUT BIT）； END COMPONENT;
COMPONENT INV PORT（X：IN BIT；z：OUT BIT）； END COMPONENT; BEGIN
U0：INV PORT MAP (water，I1)； U1：INV PORT MAP (smoke，I2)； U2：INV PORT MAP (door，I3)；
U3：NOR2 PORT MAP (i1，alarm_en，water_alarm)； U4：NOR2 PORT MAP (i2，alarm_en，smoke_alarm)； U5：NOR2 PORT MAP (i3，alarm_en，burg_alarm)； END alarm_arc；
[解] 这部分VHDL程序实现了房间内的水，烟，房门的报警功能。以水为例，设水溢出的状态为“1”，若alarm_en处于低电平使能状态，则或门U3输出的为高电平，为水溢出报警状态。若alarm_en处于高电平，则无论有否报警信号，三个输出始终为“0”，即不允许报警工作状态。这部分的VHDL程序属于结构描述，对应的逻辑电路如图解3.23所示。
器件的逻辑功能。
smoke U0 water 1 U1 1 U2 1 alarm_en 图解3.23 i2 i1 U3 water_alarm ≥1 door_alarm U4 smoke_alarm ≥1 U5 ≥1 door i3 3.23 试VHDL语言描述本章的半加器、全加器、比较器、译码器、多路选择器等
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[解] 半加器参考程序如下 achitecture func of halfadder is signal indate: std_logic_vector; begin
indate <= a & b; process(indate) begin
case indate is
when ”00” => sc <= “00”; when “01” => sc <= ”10”; when “10” => sc <= ”10”; when “11” => sc <= ”01”; end case; end process; end func;
全加器参考程序如下
achitecture func of fulfadder is signal indate: std_logic_vector; begin
indate <= a & b & ci_1; process(indate) begin
case indate is
when ”000” => sc <= “00”; when “001” => sc <= ”10”; when “010” => sc <= ”10”; when “011” => sc <= ”01”; when “100” => sc <= ”10”; when “101” => sc <= ”01”; when “110” => sc <= ”01”; when “111” => sc <= ”11”; end case; end process; end func;
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比较器参考程序如下 entity compare is
port ( a,b:in bit;c:out bit); end compare;
architecture struct of compare is signal i: bit;
component xr2 port (x,y:in bit;z:out bit); end component;
component inv port(x:in bit;z:out bit) end component; begin
u0:xr2 port map (a,b,i); u1:inv port map(I,c); end struct;
译码器参考程序如下
ARCHITECTURE rt1 OF decoder3_8 IS
SIGNAL indate: STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
indate <= A2 & A1 & A0; PROCESS(indate, STA,STB,STC)
BEGIN
IF (STA='1' AND STB='0' AND STC='0') THEN
CASE indate IS
WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \
WHEN OTHERS => Y <= \
END CASE; ELSE
Y <= \
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END IF; END PROCESS; END rt1;
多路选择器参考程序如下
ARCHITECTURE maxpld OF selsig IS BEGIN
WITH address SELECT y <= d0 WHEN 0, d1 WHEN 1,
d2 WHEN 2, d3 WHEN 3; END maxpld;
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