a
FEATURES
Signal-to-Noise Ratio: 69 dB @ fIN = 31 MHz
Spurious-Free Dynamic Range: 85 dB @ fIN = 31 MHzIntermodulation Distortion of –75 dBFS @ fIN = 140 MHzENOB = 11.1 @ fIN = 10 MHz
Low-Power Dissipation: 475 mWNo Missing Codes Guaranteed
Differential Nonlinearity Error: 0.6 LSBIntegral Nonlinearity Error: 0.6 LSBClock Duty Cycle Stabilizer
Patented On-Chip Sample-and-Hold with Full Power Bandwidth of 750 MHz
Straight Binary or Two’s Complement Output Data28-Lead SSOP, 48-Lead LQFP
Single 5 V Analog Supply, 3 V/5 V Driver SupplyPin-Compatible to AD9220, AD9221, AD9223,AD9224, AD9225
PRODUCT DESCRIPTION
The AD9226 is a monolithic, single-supply, 12-bit, 65 MSPSanalog-to-digital converter with an on-chip, high-performancesample-and-hold amplifier and voltage reference. The AD9226uses a multistage differential pipelined architecture with a pat-ented input stage and output error correction logic to provide12-bit accuracy at 65 MSPS data rates. There are no missingcodes over the full operating temperature range (guaranteed).The input of the AD9226 allows for easy interfacing to bothimaging and communications systems. With a truly differentialinput structure, the user can select a variety of input ranges andoffsets including single-ended applications.
The sample-and-hold amplifier (SHA) is well suited for IFundersampling schemes such as in single-channel communi-cation applications with input frequencies up to and wellbeyond Nyquist frequencies.
The AD9226 has an on-board programmable reference. For sys-tem design flexibility, an external reference can also be chosen.A single clock input is used to control all internal conversioncycles. An out-of-range signal indicates an overflow conditionthat can be used with the most significant bit to determine lowor high overflow.
REV.0
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Complete 12-Bit, 65 MSPS
ADC Converter
AD9226
FUNCTIONAL BLOCK DIAGRAM
OTRBIT 1(MSB)BIT 12(LSB)
MODE
AVSS
DRVSS
The AD9226 has two important mode functions. One will setthe data format to binary or two’s complement. The second willmake the ADC immune to clock duty cycle variations.
PRODUCT HIGHLIGHTS
IF Sampling—The patented SHA input can be configured foreither single-ended or differential inputs. It will maintain out-standing AC performance up to input frequencies of 300 MHz.Low Power—The AD9226 at 475 mW consumes a fraction ofthe power presently available in existing, high-speed monolithicsolutions.
Out of Range (OTR)—The OTR output bit indicates whenthe input signal is beyond the AD9226’s input range.
Single Supply—The AD9226 uses a single 5 V power supplysimplifying system power supply design. It also features a sepa-rate digital output driver supply line to accommodate 3V and5V logic families.
Pin Compatibility—The AD9226 is similar to the AD9220,AD9221, AD9223, AD9224, and AD9225 ADCs.
Clock Duty Cycle Stabilizer—Makes conversion immune tovarying clock pulsewidths.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781/329-4700World Wide Web Site: Fax: 781/326-8703© Analog Devices, Inc., 2000
AD9226–SPECIFICATIONS
DC SPECIFICATIONS
Parameter
RESOLUTION
ACCURACY
Integral Nonlinearity (INL)Differential Nonlinearity (DNL)No Missing Codes GuaranteedZero ErrorGain Error
TEMPERATURE DRIFTZero ErrorGain Error1Gain Error2POWER SUPPLY REJECTIONAVDD (5 V ± 0.25 V)INPUT REFERRED NOISEVREF = 1.0 VVREF = 2.0 VANALOG INPUT
Input Span (VREF = 1 V)
(VREF = 2 V)
Input (VINA or VINB) RangeInput Capacitance
INTERNAL VOLTAGE REFERENCEOutput Voltage (1 V Mode)
Output Voltage Tolerance (1 V Mode)Output Voltage (2.0 V Mode)
Output Voltage Tolerance (2.0 V Mode)
Output Current (Available for External Loads)Load Regulation3REFERENCE INPUT RESISTANCEPOWER SUPPLIESSupply VoltagesAVDDDRVDDSupply CurrentIAVDD4
IDRVDD
5
(AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS, VREF = 2.0 V, Differential inputs, TMIN to TMAX unless otherwisenoted.)
Temp
Test Level
Min12
Full25°CFull25°CFullFull25°C25°CFullFullFullFullFull25°CFullFullFullFullFullFullFull25°CFull25°CFullFull25°CFull
VIVIIVIIVVVVVIVVVVIVVVIVIVVIV
±0.6
±1.6
±0.6
±1.0
12
±0.3
±1.4±2.0
±0.6±2±26±0.4±0.05
±0.4
0.50.2512
71.0
±15
2.0
±29
1.00.7
1.5
5
AVDD
Typ
Max
UnitBitsLSBLSBLSBLSBBits% FSR% FSR% FSR% FSRppm/°Cppm/°Cppm/°C% FSR% FSRLSB rmsLSB rmsV p-pV p-pVpFVmVVmVmAmVmVk