Figure 9b.Alternate AC-Coupled Input Configuration
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0.5
1.0
1.5
2.0
2.5volts
3.0
3.5
4.0
4.5
5.0
Figure 10.THD vs. Common-Mode Voltage(2 V Differential Input Span, fIN = 10 MHz)
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sets the input span to be 1.5 V p-p. The midscale voltage canalso be set to VREF by connecting VINB to VREF. Alterna-tively, the midscale voltage can be set to 2.5 V by connectingVINB to a low-impedance 2.5 V source as shown in Figure 12.
Figure 12.Resistor Programmable Reference (1.5 V p-pInput Span, Differential Input VCM = 2.5 V)USING AN EXTERNAL REFERENCE
Figure 11a.Equivalent Reference Circuit
Figure 11b.CAPT and CAPB DC-Coupling
The AD9226 contains an internal reference buffer, A2 (seeFigure 11b), that simplifies the drive requirements of an externalreference. The external reference must be able to drive about5k (±20%) load. Note that the bandwidth of the referencebuffer is deliberately left small to minimize the reference noisecontribution. As a result, it is not possible to rapidly change thereference voltage in this mode.
Figure 13 shows an example of an external reference drivingboth VINB and VREF. In this case, both the common-modevoltage and input span are directly dependent on the value ofVREF. Both the input span and the center of the input span areequal to the external VREF. Thus the valid input range extendsfrom (VREF + VREF/2) to (VREF – VREF/2). For example,if the REF191, a 2.048 V external reference, is selected, theinput span extends to 2.048 V. In this case, 1 LSB of the AD9226corresponds to 0.5mV. It is essential that a minimum of a 10 µFcapacitor, in parallel with a 0.1 µF low-inductance ceramiccapacitor, decouple the reference output to ground.
To use an external reference, the SENSE pin must be connectedto AVDD. This connection will disable the internal reference.
The actual reference voltages used by the internal circuitry of theAD9226 appear on the CAPT and CAPB pins. The voltageson these pins are symmetrical about the analog supply. Forproper operation when using an internal or external reference, itis necessary to add a capacitor network to decouple these pins.Figure 11b shows the recommended decoupling network. Theturn-on time of the reference voltage appearing between CAPTand CAPB is approximately 10 ms and should be evaluated inany power-down mode of operation.
USING THE INTERNAL REFERENCE
The AD9226 can be easily configured for either a 1 V p-p inputspan or 2 V p-p input span by setting the internal reference.Other input spans can be realized with two external gain-setting resistors as shown in Figure 12 of this data sheet, orusing an external reference.
Pin Programmable Reference
By shorting the VREF pin directly to the SENSE pin, the inter-nal reference amplifier is placed in a unity-gain mode and theresultant VREF output is 1 V. By shorting the SENSE pindirectly to the REFCOM pin, the internal reference amplifier isconfigured for a gain of 2.0 and the resultant VREF output is2.0 V. The VREF pin should be bypassed to the REFCOM pinwith a 10 µF tantalum capacitor in parallel with a low-inductance0.1 µF ceramic capacitor as shown in Figure 11b.
Resistor Programmable Reference
Figure ing an External Reference
MODE CONTROLSClock Stabilizer
Figure 12 shows an example of how to generate a reference
voltage other than 1.0 V or 2.0 V with the addition of two exter-nal resistors. Use the equation,
VREF = 1 V × (1 + R1/R2)
to determine appropriate values for R1 and R2. These resistorsshould be in the 2 k to 10 k range. For the example shown,R1 equals 2.5 k and R2 equals 5 k . From the equation above,the resultant reference voltage on the VREF pin is 1.5 V. This
The clock stabilizer is a circuit that desensitizes the ADC fromclock duty cycle variations. The AD9226 eases system clockconstraints by incorporating a circuit that restores the internal dutycycle to 50%, independent of the input duty cycle. Low jitter onthe rising edge (sampling edge) of the clock is preserved whilethe noncritical falling edge is generated on-chip.
It may be desirable to disable the clock stabilizer, and may benecessary when the clock frequency speed is varied or completely
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stopped. Once the clock frequency is changed, over 100 clock
Table IV.Output Data Format
DIGITAL INPUTS AND OUTPUTSDigital Outputs
Table IV details the relationship among the ADC input, OTR, andstraight binary output.
Figure 15.Overrange or Underrange Logic
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