CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readilyaccumulate on the human body and test equipment and can discharge without detection. Althoughthe AD9226 features proprietary ESD protection circuitry, permanent damage may occur ondevices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions arerecommended to avoid performance degradation or loss of functionality.
REV. 0–5–
AD9226
PIN CONNECTION48-Lead LQFP
MODE1CAPTCAPTCAPBCAPBREF COM (AVSS)
PIN CONNECTION28-Lead SSOP
VREF
VINBVINACM LEVELNC
VR
AVSSAVSSAVDDAVDD
SENSE
NCNCCLKNCOEBNCNC(LSB) BIT 12MODE2AVDDAVSSAVSS
AVDDDRVSSDRVDDOTR
BIT 1 (MSB)
BIT 2BIT 3
BIT 11
DRVSSDRVDDBIT 10BIT 9
DRVDDBIT 4
DRVSS
BIT 8BIT 7BIT 6BIT 5
48-PIN FUNCTION DESCRIPTIONS
28-PIN FUNCTION DESCRIPTIONS
Pin
Number1, 2, 32, 333, 4, 31, 345, 6, 8, 10,11, 44791213
14, 22, 3015, 23, 2916–21,24–2627283536373839, 4041, 424345464748
NameAVSSAVDDNCCLKOEBBIT 12BIT 11DRVSSDRVDDBITS 10–5,BITS 4–2BIT 1OTRMODE2SENSEVREFREFCOM(AVSS)CAPBCAPTMODE1CM LEVELVINAVINBVR
DescriptionAnalog Ground5 V Analog SupplyNo Connect
Clock Input Pin
Output Enable (Active Low)Least Significant Data Bit (LSB)Data Output Bit
Digital Output Driver Ground3 V to 5 V Digital OutputDriver SupplyData Output Bits
Most Significant Data Bit (MSB)Out of Range
Data Format SelectReference SelectReference In/OutReference CommonNoise Reduction PinNoise Reduction PinClock Stabilizer
Midsupply ReferenceAnalog Input Pin (+)Analog Input Pin (–)Noise Reduction Pin
Pin
Number123–12131415, 2616, 2517181920212223242728
NameCLKBIT 12BITS 11–2BIT 1OTRAVDDAVSSSENSEVREFREFCOM(AVSS)CAPBCAPTMODEVINAVINBDRVSSDRVDD
Description
Clock Input Pin
Least Significant Data Bit (LSB)Data Output Bits
Most Significant Data Bit (MSB)Out of Range
5 V Analog SupplyAnalog GroundReference Select
Input Span Select (Reference I/O)Reference Common
Noise Reduction PinNoise Reduction Pin
Data Format Select/Clock StabilizerAnalog Input Pin (+)Analog Input Pin (–)
Digital Output Driver Ground3 V to 5 V Digital OutputDriver Supply
–6–REV. 0
AD9226
DEFINITIONS OF SPECIFICATIONSINTEGRAL NONLINEARITY (INL)
EFFECTIVE NUMBER OF BITS (ENOB)
INL refers to the deviation of each individual code from a linedrawn from “negative full scale” through “positive full scale.”The point used as “negative full scale” occurs 1/2 LSB beforethe first code transition. “Positive full scale” is defined as a level1 1/2 LSB beyond the last code transition. The deviation ismeasured from the middle of each particular code to the truestraight line.
DIFFERENTIAL NONLINEARITY (DNL, NO MISSINGCODES)
For a sine wave, SINAD can be expressed in terms of the num-ber of bits. Using the following formula,
N = (SINAD – 1.76)/6.02
it is possible to obtain a measure of performance expressed asN, the effective number of bits.
Thus, effective number of bits for a device for sine wave inputsat a given input frequency can be calculated directly from itsmeasured SINAD.
TOTAL HARMONIC DISTORTION (THD)
An ideal ADC exhibits code transitions that are exactly 1 LSBapart. DNL is the deviation from this ideal value. Guaranteedno missing codes to 12-bit resolution indicates that all 4096codes, respectively, must be present over all operating ranges.
ZERO ERROR
THD is the ratio of the rms sum of the first six harmonic com-ponents to the rms value of the measured input signal and isexpressed as a percentage or in decibels.
SIGNAL-TO-NOISE RATIO (SNR)
The major carry transition should occur for an analog value1/2 LSB below VINA = VINB. Zero error is defined as thedeviation of the actual transition from that point.
GAIN ERROR
SNR is the ratio of the rms value of the measured input signal tothe rms sum of all other spectral components below the Nyquistfrequency, excluding the first six harmonics and dc. The valuefor SNR is expressed in decibels.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
The first code transition should occur at an analog value1/2 LSB above negative full scale. The last transition shouldoccur at an analog value 1 1/2 LSB below the positive full scale.Gain error is the deviation of the actual difference between firstand last code transitions and the ideal difference between firstand last code transitions.
TEMPERATURE DRIFT
SFDR is the difference in dB between the rms amplitude of theinput signal and the peak spurious signal.
ENCODE PULSEWIDTH DUTY CYCLE
The temperature drift for zero error and gain error specifies themaximum change from the initial (25°C) value to the value atTMIN or TMAX.
POWER SUPPLY REJECTION
Pulsewidth high is the minimum amount of time that the clockpulse should be left in the logic “1” state to achieve rated per-formance; pulsewidth low is the minimum time the clock pulseshould be left in the low state. At a given clock rate, these specsdefine an acceptable clock duty cycle.