基于VHDL的多路抢答器的设计(5)

2018-12-23 00:32

2009届电子信息工程(应用电子技术方向)专业毕业设计(论文)

STATES<=\ELSIF (CLK 'EVENT AND CLK='1' )THEN

IF ( WARN='0' )THEN

IF ( S3 ='1' AND S2='0' AND S1='0' AND S0='0' ) THEN STATES <= \

ELSIF ( S2 ='1' AND S3='0' AND S1='0' AND S0='0' ) THEN STATES <= \

ELSIF ( S1 ='1' AND S3='0'AND S2='0' AND S0='0') THEN STATES <= \

ELSIF ( S0 ='1'ANDS3='0' AND S2='0' AND S1='0' ) THEN STATES <= \ELSE STATES<=\END IF ;

END IF ;

END IF ;

END PROCESS ;

END ARCHITECTURE ;

2、报警模块源代码 (1)LIBRARY IEEE; USE

IEEE.STD_LOGIC_1164.ALL;

ENTITY ALARM IS

PORT(CLEAR,WARN: IN STD_LOGIC;

SOUND: OUT STD_LOGIC);

END ALARM;

ARCHITECTURE FOUR OF ALARM IS BEGIN

(2)LIBRARY IEEE;

PROCESS(WARN,CLEAR) BEGIN

IF CLEAR='1' THEN SOUND<='0'; ELSIF WARN='1' THEN

SOUND<='1'; ELSE SOUND<='0'; END IF;

END PROCESS;

END ARCHITECTURE ;

17

文超:基于VHDL的多路抢答器的设计

USE

IEEE.STD_LOGIC_1164.ALL;

ENTITY FOUL IS

PORT(CLEAR : IN STD_LOGIC;

S0,S1,S2,S3: IN STD_LOGIC;

LEDE: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); WARNS: OUT STD_LOGIC);

END FOUL;

ARCHITECTURE ONE OF FOUL IS BEGIN

PROCESS(CLEAR,S0,S1,S2,S3)

VARIABLE a : Std_Logic_Vector (3 DOWNTO 0); BEGIN

a := S3 & S2 & S1 & S0 ; CASE a IS

WHEN \WHEN \WHEN \WHEN \WHEN OTHERS =>LEDE <=\END CASE ;

ELSE LEDE<=\END IF;

IF CLEAR='1' THEN

END PROCESS;

END ONE;

3、计分模块源代码 LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY SCORE IS

PORT(CLK,SUB,ADD,CLR:IN STD_LOGIC;

CHOOSE: IN STD_LOGIC_VECTOR(3 DOWNTO 0);

aa0,aa1,bb0,bb1,cc0,cc1,dd0,dd1: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0));

END SCORE;

ARCHITECTURE RTL OF SCORE IS BEGIN

PROCESS( CHOOSE , CLK ,SUB , ADD ,CLR)

BEGIN

18

2009届电子信息工程(应用电子技术方向)专业毕业设计(论文)

IF(CLR='1') THEN

aa1<=\bb1<=\cc1<=\dd1<=\IF(ADD='1') THEN

IF(CHOOSE=\

IF(aa0=\

aa0<=\IF(aa1=\aa1<=\ELSE

aa1<=aa1+'1'; END IF; aa0<=aa0+'1';

ELSIF(CLK'EVENT AND CLK='1') THEN

ELSE END IF;

IF(bb0=\

bb0<=\IF(bb1=\bb1<=\ELSE

bb1<=bb1+'1'; END IF;

bb0 <= bb0+'1';

ELSIF (CHOOSE=\

ELSE END IF;

IF(cc0=\

cc0<=\

IF(cc1=\cc1<=\ELSE

cc1<=cc1+'1'; END IF;

ELSIF( CHOOSE=\

ELSE

19

文超:基于VHDL的多路抢答器的设计

END IF;

IF(dd0=\

dd0<=\IF(dd1=\dd1<=\ELSE

dd1<=dd1+'1'; END IF; dd0<=dd0+'1';

ELSIF (CHOOSE=\

ELSE END IF;

END IF;

IF(CHOOSE=\

IF(aa0=\

IF(aa1=\

aa0<=\aa1<=\aa0<=\aa1<=aa1-'1';

ELSIF(SUB='1') THEN

ELSE

END IF; aa0<=aa0-'1';

ELSE END IF;

IF(bb0=\

IF(bb1=\

bb0<=\bb1<=\bb0<=\bb1<=bb1-'1';

ELSIF (CHOOSE=\

ELSE

END IF; bb0<=bb0-'1';

ELSE END IF;

20

2009届电子信息工程(应用电子技术方向)专业毕业设计(论文)

ELSIF(CHOOSE=\

IF(cc0=\

IF(cc1=\

cc0<=\cc1<=\cc0<=\cc1<=cc1-'1';

ELSE

END IF; cc0<=cc0-'1';

ELSE END IF;

IF(dd0=\

IF(dd1=\

dd0<=\dd1<=\dd0<=\dd1<=dd1-'1';

ELSIF(CHOOSE=\

ELSE

END IF; dd0<=dd0-'1';

ELSE END IF;

END IF;

END IF; END IF ;

END PROCESS;

END ARCHITECTURE ;

21


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