Integrated PCM Codec
KUL B. OHRI AND MICHAEL J.CALLAHAN, JR., MEMBER,lEEE
Abstract–A one-chip PCM codec circuit has been implemented in the CMOS process. The design uses two separate linear digital-to-analog converters, made with charge redistribution techniques.
Experimental results show tbe circuit to meet accepted requirements and operate with very low power requirements. SINGLE-CHIP CMOS PCM CODEC
THE processing of voice signals in a digital manner is becoming more popular. There are several contending modulation schemes including pulse-width modulation
(PWM),pulse-amplitude modulation (PAM), delta modulation, and pulse-code modulation (PCM).
A specific PCM approach [1] has become the standard in North America. There are two separate types of applications for this time-division multiplex scheme: transmission and digital voice switching. Transmission involves sending the voice data in digital form from one location to another. Since the transmit and receive circuitry are separated from one another, some sort of synchronization is implied in this
scheme. Applications of this type are concentrators and channel banks.
Switching involves only the connection of one voice channel to another in a digital mamner. This scheme has the transmit and receive circuitry in close proximity so that clocking and synchronization may be done by one common circuit. Important applications of this type are electronic PABX and digital central offices.
In the system defined by [1], the analog input signal is sampled at an 8 kHz rate. Fig. 1 shows a 1 kHz input sampled in this manner. At each of these sampling times, the analog information is converted into an 8-bit digital word that is transmitted in serial format at a 1.544 Mbit/s rate.
Fig. 2 shows twenty-four voice channels which are timedivision multiplexed onto one pair of wires. (For simplicity,
only simplex operation is shown.) Each channel is first bandlimited to less than 4 kHz by the XMIT tilter, then sampled
and converted to a companded digital code. The 8-bit words are transmitted serially to a multiplexer.The bit stream of 1.544 Mbits/s is sent to a demultiplexer where the appropriate A~(lZ=l, 2, ““ “ 24) channel is connected to the BM(rrz = 1, 2,””” 24) channel. This selection is done by the main computer,
sometimes known as common control.
For transmission applications, the digital PCM data might be transmitted between two central offices. For switching applications, such as for a PBX, this technique allows for connection of two voice paths digitally. Digital switching obviates the need for low on-resistance analog switches.
Manuscript received June 5, 1978; revised September 11, 1978. The authors are with MOSTEK Corporation, Carrollton, TX 75006.
The process selected for this device is metal-gate CMOS. This technology allows for very low power digital circuitry and easier analog design than single-polarity MOS. This process selection requires the need for two supplies, plus and minus 5V. To minimize power, all the digital logic is operated from the positive supply with respect to ground. Only the analog
section (one amplifier and one comparator) operates from the plus and minus supplies. CHIP ARCHITECTURE
Fig. 3 shows the block diagram representation of the codec circuit. The important features of the scheme used are listed below.
1) Two independent DAC’S for encode and decode functions provide system isolation not achievable using shared DAC approach. The capacitive two DAC approach also eliminates external sample/hold capacitors as well as external filter for autozeroing required in shared DAC approach. This minimizes external components required. 2) Complete signaling compatibility with D3 channel bank requirements.
3) The number of analog components used are the minimum required for system
implementation, namely two: one comparator and only one op amp on the entire circuit. Minimizing the linear components helps reduce system operating power which was the overriding consideration in circuit design.
Using the CMOS process, the digital portions consume power only during transitions. The linear sections consume power continuously.
4) The digital commanding section allows easy conversion from p-law to A-law. Synchronous/asynchronous data input/output rates from 128 kHz to 2.048 MHz are possible with negligible change in power dissipation.
MODES OF OPERATION
The XMIT and receive function are completely independent of each other and of the master clock. Thus the chip can operate in synchronous/asynchronous mode at various input/output clock rates. The chip timing diagram is shown in Fig.4 and the receive and XMIT modes of operation are described in detail below.
A. Receive Mode of Operation
In the receive mode of operation, the serial input data are shifted into the input buffer at the receive clock rate during the period when receive sync is high. The translated data from the 8- to 13-bit converter are latched into the 13-bit receive latch which updates the output of the receive DAC with 100
percent duty cycle. The receive DAC acts as a sample and hold and is buffered by the unity-gain op amp to the output.
During the signaling frame a 7-bit decode is performed and the eighth data bit is latched into the SigA/SigB output latch as selected by the A/B select (RCV) input. When the eighth bit of a word is a signaling bit, it is assigned the value of 1/2 step.This results in a lower S/D ratio than if it were arbitrarily set to either a one or zero. The circuit of Fig. 5 shows the implementation of 7-bit/8-bit decode. For frames one through five and seven through eleven, input A is 1. Bit 8 corresponds to Q7 output and during decode B is 1; thus output C is O, resulting in 8-bit decode.For frames six and twelve, input A is O which results in bit 8 being O and output C’, corresponding
to 1/2 step offset control,being 1. This results in a 7-bit decode with an effective 1/2 step offset during signaling frames and $1-bit decode during other frames.
B. Transmit Mode of Operation
In this mode of operation the analog signal is sampled in the input sample/hold which performs the autozero function simultaneously as described in the circuit operation section.Following the hold mode, the encoding process is completed using the successive approximation technique. The operation of the XMIT DAC is similar to the operation of the receive
DAC as described earlier.
After the encode process is completed, the output of the SAR is loaded into the output buffer. The data are transmitted
serially at the output clock rate during the period when the XMIT sync is high. During the signaling frame, signaling information (SigA/SigZ3) is inserted into the output bit stream in place of the eighth data bit as selected by the A/B select (XMIT) input. The circuit of Fig. 6 describes the insertion of the signaling
bit on the outgoing digital bit stream. For frames one through five and seven through eleven, node B is 1 and D4 corresponds to Q5. During frames six and twelve, node B goes low for 1 XMIT clock period thus switching
signaling information to the D-input of Q4, and is registered at its output on the next positive clock edge.
Since input A is only one clock period wide, as shown, Q4 is modified only once at the period Q7 which would normally appear at its input after the second clock edge and prior to the third clock edge. Thus the outgoing data stream has signaling information