added as the eighth bit only during the sixth and the twelfth frames and is unchanged during the remaining frames.
CIRCUIT DESCRIPTION
The system timing is controlled by the sequence controller which operates at a master clock of 1.544-2.048 MHz. All necessary signals, e g., autozero, sample-and-hold, clocksuccessive approximation register (@sAR), encode/decode control,etc., are generated in this section.
The 8- to 13-bit converter gives a one-to-one translation between
8.bit companded code at its input to a 13-bit linear code at its output, thus allowing the use of a binary DAC in the digit al-to-analog conversion process. Fig. 7 shows the time-sharing approach used to allow both the encode and the decode DAC’S to share the 8- to 13-bit conversion logic.
The rising edge of the XMIT sync starts @sAR. Similarly decode interrupt is generated on the falling edge of the RCV sync.
To insure proper encoding, three conditions need to be satisfied.
1) Decode/encode should go high at least a time T/2 after the decode interrupt is initiated. Thus even if @sARand decode interrupt overlap, the encoder has access to the 8- to 13-bit converter for a period of at least T/2 during which time the converted data are latched into the 13-bit encode latch.
2) @sAR is kept low until decode interrupt goes low. This extends the encode time for that encode approximation and at the same time insures the decoder has access to the 8- to 13-bit code converter for a period (Tl) long enough to fiiish the conversion process. 3) @sAR is extended if @sAR is low and the decode interrupt is high. CODE -CONVERSION LOGIC
Table I shows the codes for an ideal decode function. Since the accuracy required in each chord is only ~ step size in that chord, the accuracy requirements reflected for a linear DAC are only 5 bits linearity in chord O and 6 bits linearity in chords 1 through 7. Thus the binary DAC needs to have 13 bits of resolution and only 6 bits linearity to satisfy system accuracy Requirements.
Table II shows the actual codes implemented. The only dif- where CO through CT corresponds to chords Othrough 7, SI through S,4 corresponds to step inputs. ference between the two code tables is the count of 1 for codes of 1023 and higher. This adds negligible performance degradation
while considerably simplifying the circuit implementation.
Table II can be simplified for each bit weight of the binary DAC. For example, for bit 7 with a bit weight of 64 units,the bit 7 ON/OFF table is shown in Table 111. The expression for bit 7 can be written as follows:
where
CO through C7 corresponds to chords Othrough 7, SI through S4 corresponds to step inputs.
Since CO through CT are mutually exclusive, bit 7 can be implemented using transmission gates, as shown in Fig. 8.Similar expression can be derived for the remaining bits of the binary DAC. DIGITAL-TO-ANALOG CONVERTER DESIGN
The 13-bit binary DAC operates on the charge distribution [2] principal of a binary weighted capacitor ladder. The DAC
circuit schematic is shown in Fig. 9. As shown in Fig. 9, the capacitor ladder has two sections of 7 bits (7 most significant bits) and 6 bits (6 least significant bits) connected b y a 64:1 capacitor divider. The equivalent circuit of the two sections can be drawn, as shown in Fig. 10.
The output of the DAC can be written as
which is equivalent to the output of a 13-bit DAC with an equivalent output capacitance of 128 pF. ENCODER
The equivalent ladder capacitor of 128 pF is employed to perform the additional function of autozero and sample-and. hold in the encoder. This is shown in Fig. 11.
Initially S1 is connected to YIN and S2 is closed. The opamp A 1 is operating as a unity-gain follower and its offset voltage (VOFF) is stored on the capacitor.Then switch S2 is opened and S1 is switched to analog ground. The voltage at the inverting input of the op amp is now VOFF-VIN. Thus when the amplifier A 1 operates with S2 open it acts as a comparator with effectively zero offset and – VIN applied on its inverting input. (Input offset of amplifier A2 as reflected at the A 1 amplifier input is effectively
VoFF2/A 1.) The other end of the capacitor can now be oper-ated as a DAC. Thus ‘the capacitor ladder performs all the necessary functions of autozero, sample-and-hold, as well as a DAC in the encode section of the chip.
The comparator has been divided into two amplifying sections to obtain 1) AIA2 product> 104
2) stable operation during the autozero cycle.
Amplifier A ~ is designed to provide stable operation during the autozero cycle when it essentially operates as a unity-gain follower. Amplifier AZ is used to achieve a minimum gain of 104 for the comparator. This allows a resolution of ~ step in chord O thus insuring that the coded output is always stable.Idle channel noise measured with no signaling is typically 5 dBrnCO using this scheme.
EFFECT OF NONIDEALITIES ON CODER PERFORMANCE
The nonidealities of components deteriorates the system performance. Some of the important nonidealities are described below:
1) Effect of Stray Capacitance Loading on DAC Output: Referring to Fig. 10, stray capacitance loading (CL) on the DAC output gives the following modified expression for VDAC circuit schematic is shown in Fig. 9. As shown in Fig. 9, the capacitor ladder has two sections of 7 bits (7 most significant bits) and 6 bits (6 least significant bits) connected b y a 64:1
capacitor divider. The equivalent circuit of the two sections can be drawn, as shown in Fig. 10.The output of the DAC can be written as
which is equivalent to the output of a 13-bit DAC with an equivalent output capacitance of 128 pF. ENCODER
The equivalent ladder capacitor of 128 pF is employed to perform the additional function of autozero and sample-and.hold in the encoder. This is shown in Fig. 11.
Initially ~1 is connected to YIN and S2 is closed. The opamp A 1 is operating as a unity-gain follower and its offset voltage (VOFF) is stored on the capacitor.
Then switch S2 is opened and S1 is switched to analog ground. The voltage at the inverting input of the op amp is now VOFF-VIN. Thus when the amplifier A 1 operates with S2 open it acts as a comparator with effectively zero offset and – VIN applied on its inverting input. (Input offset of amplifier A2 as reflected at the A 1 amplifier input is effectively
VoFF2/A 1.) The other end of the capacitor can now be oper-ated as a DAC. Thus ‘the capacitor ladder performs all the
necessary functions of autozero, sample-and-hold, as well as a DAC in the encode section of the chip.
The comparator has been divided into two amplifying sections to obtain
1) AIA2 product> 104
2) stable operation during the autozero cycle.
Amplifier A ~ is designed to provide stable operation during the autozero cycle when it essentially operates as a unity-gain follower. Amplifier AZ is used to achieve a minimum gain of 104 for the comparator. This allows a resolution of ~ step in chord O thus insuring that the coded output is always stable. Idle channel noise measured with no signaling is typically 5 dBrnCO using this scheme.
The nonidealities of components deteriorates the system
performance. Some of the important nonidealities are described below:
Effect of Stray Capacitance Loading on DAC Output:
Referring to Fig. 10, stray capacitance loading (CL) on the DAC output gives the following modified expression for VDAC: VDAC =(1 - CL/128) Thus the DAC output CL/128).
is modified by the gain factor (1 -
In the encoder, since the analog input also goes through the same gain factor, gain error is completely eliminated. In the decoder, however, there is a constant gain factor of (1 - CL/128). For CL = 1.28 pF (1 percent CLADDER) a fixed
gain error of -0.087 dB is introduced. Typical gain tracking error measured is -0.1 dB. Figs. 16 and 17 show the measured system performance.
Because of the extremely small temperature coefficient of