the capacitors, system performance is maintained well above D3 specifications over - 55°C to +1OO”C temperature range. Long term stability is excellent for simflar reasons. 2) Effect of Mismatch of 1.016 pF Divider Capacitance:
The deviation of the divider capacitance from the desired ratio of 1.016:1 introduces both gain and linearity errors. Assuming fA C variation in the value of 1.016:1 capacitance ratio, the
output of the DAC will be modified to the expression given below:
Thus the AC error of +1.6 percent is capable of introducing an error of ~ step size in chords Oand 1, ~ step size in chord 2, and is negligible thereafter. Keeping the AC error below +1 percent coupled with 6-bit linearity requirements for the 13- bit DAC is sufficient to insure system accuracy requirements. Typically 10.1 percent capacitance ratio is easily achievable, thus making this error term negligible.
3) Reference Source Mismatch and Stability: The use of
external references allows the user to control this important source of gain error and long term stability. The quality of external reference sources used directly reflects on the coder gain tracking and long term stability as otherwise the coder is capable of providing -0.1 dB gain tracking error with excellent long term stability. By adding a unity-gain inverting amplifier to the chip, a single reference supply would suffice. However, the nonideality of this unity-gain inverting amplifier will add
to system gain and signaI-to-distortion errors which is bettercontrolled by the user by employing this unity-gain inversion externally.
COMPARATORAND UNITY -GAIN AMPLIFIER CIRCUITS Unity-Gain Amplifier Circuit
The unity-gain amplifier consists of two-stages of amplification with Miller- capacitive compensation, as shown in Fig. 12.
The first stage consisting of transistors Ml, M2, M3, and M5 is a basic differential amplifier with a typical gain of 40 dB.
The second stage consisting of Ml O and 13 provides a typical gain of 35 dB, as well as level translation. CFB is the Miller feedback capacitance (20 pF) used for unity-gain frequency compensation. Transistor Q1 eliminates the feedforward from the first amplifying stage to the second amplifying stage.
Transistors M4, M6, M7, M8, and M9 improve the +5 V PSRR by providing a common-mode feedback loop in the
first amplifying stage. Assuming that the +5 V supply increases, M6 and M7 conduct more causing M4, M3, and M5 to conduct more which pulls the gates of M6, M7, and Ml O towards the +5 V supply, thus forcing a constant VGS on Ml O. This common-mode loop has a gain of approximately 40 dB, thus improving +5 V PSRR by about 40 dB,
The amplifier has a slew rate of approximately 2 V/ps and a unit y-gain crossover frequency of approximately 1.5 MHz. Comparator Circuit
As mentioned previously, the comparator consists of two separate amplifiers A 1 and .42. The amplifier A 1 circuit schematic is shown in Fig. 13. Amplifier A2 has a similar design with the exception that its output stage provides
unipolar output swing of O to +5 V as opposed to amplifier.41 which has bipolar outputs.
Amplifier .41 consists of two stages. The first stage consisting of transistors Ml 1,M12,M13,M14, Ml 5, and M16 is a differentail
stage designed to provide improved gm and thus improve slew rate for the comparator circuit. As shown in Fig. 13 transistors Ml 3 and Ml 6 have a 2AI change in current while Ml 1 and Ml 2 have only a AI change, thus providing a factor of 2 improvement in output slew rate.
The second stage consists of transistors Ml 7, Ml 8, M19, and current source M21. The current mirror consisting of
transistors Ml 8 and Ml 9 provides another current amplification of 5. Current source M21 has a source degeneration
resistance of 6 Ml which boosts the output impedance by a factor of 4 thus improving the amplifier gain by 6 dB. All amplification (approximately 52 dB) is achieved in the
output stage which has high output impedance (approximately 200 kS2).
When used as a unity-gain follower during the autozero
cycle, the ladder capacitance of 128 pF provides the dominant pole for frequency compensation thus eliminating the need for extra compensation capacitors. CAPACITOR LADDER LAYOUT
To achieve best possible matching for the capacitors in the D/A ladder, higher value capacitors were made using multiples of a 1 pF unit capacitor. For example: 1 pl? and 4 pF capacitor
layouts are shown in Fig. 14.
To achieve a theoretical ratio match of 4:1, not only was the 4 pF capacitor made equal to 4 units but the thin and thick oxide stray capacitors shown in the diagram were also made in the ratio of 4:1. The layout stray capacitors were
distributed so as to minimize the effects of mask misalignment. Thus the accuracy of the capacitor ladder so implemented will be limited by mask making tolerances and process etching errors.
EXPERIMENTAL RESULTS
The setup of Fig. 15 was used to evaluate the chip performance. The MKS 1SO codec performance exceeds the American
Telephone and Telegraph D3 channel bank specifications.
Fig. 16 shows the signal-to-quantizing distortion as a function of input level.
Idle channel noise of 13-14 dBrnCO is better than the D3 spec by 9-10 dB. Gain tracking is shown in Fig. 17.