7、程序清单
use dspbuilder.dspbuilderblock.all; library lpm;
use lpm.lpm_components.all; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; library dspbuilder; Entity biaozhun1 is
Port(clk:out std_logic;
clock
: : : : : : : :
in std_logic; in std_logic:='0';
sclrp Input
in std_logic_vector(7 downto 0); in std_logic_vector(31 downto 0); in std_logic_vector(7 downto 0); in std_logic_vector(7 downto 0); out std_logic_vector(9 downto 0); out std_logic_vector(9 downto 0)
Input1 Input2 Input3 Output Output1
);
end biaozhun1;
architecture aDspBuilder of biaozhun1 is signal SAOutputO signal SAOutput1O signal sclr signal A0W signal A1W signal A2W signal A3W signal A4W signal A5W
:
:
std_logic_vector(9 downto 0); :
std_logic_vector(9 downto 0);
std_logic:='0'; : : : : : :
std_logic_vector(32 downto 0); std_logic_vector(9 downto 0); std_logic_vector(15 downto 0); std_logic_vector(8 downto 0); std_logic_vector(32 downto 0); std_logic_vector(8 downto 0);
signal A6W signal A7W signal A8W signal A9W
: : : : : : : : : : : : :
std_logic_vector(8 downto 0); std_logic_vector(33 downto 0); std_logic_vector(23 downto 0); std_logic_vector(32 downto 0); std_logic_vector(19 downto 0); std_logic_vector(19 downto 0); std_logic_vector(33 downto 0); std_logic_vector(34 downto 0); std_logic_vector(10 downto 0); std_logic_vector(10 downto 0); std_logic_vector(10 downto 0); std_logic_vector(10 downto 0); std_logic_vector(10 downto 0);
signal A10W signal A11W signal A12W signal A13W signal A14W signal A15W signal A16W signal A17W signal A18W Begin
assert (1<0) report altversion severity Note; Output Output1
<= SAOutputO; <= SAOutput1O;
-- Global reset circuitry for the input global reset sclrp sclr
<= sclrp;
-- Input - I/O assignment from Simulink Block \A3W(7 downto 0) A3W(8)
<= Input;
<= '0';
-- Input - I/O assignment from Simulink Block \A4W(31 downto 0) A4W(32)
<= Input1;
<= '0';
-- Input - I/O assignment from Simulink Block \A5W(7 downto 0) A5W(8)
<= Input2;
<= '0';
-- Input - I/O assignment from Simulink Block \A6W(7 downto 0)
<= Input3;
A6W(8) A0W(32)
<= '0'; <= '0';
-- Constant assignment - Simulink Block \A1W(9)
<= '0';
<= \
A1W(8 downto 0)
-- Constant assignment - Simulink Block \A2W(15)
<= '0';
<= \
A2W(14 downto 0)
-- Concatenation Operation - Simulink Block \A8W(22 downto 0) <= A3W(7 downto 0) & A2W(14 downto 0); A8W(23)
<=
'0';
-- Concatenation Operation - Simulink Block \A9W(31 downto 0) <= A1W(8 downto 0) & A8W(22 downto 0); A9W(32)
<= <= '0'; <= '0'; <= '0';
'0';
A16W(10) A17W(10) A18W(10)
-- Output - I/O assignment from Simulink Block \Outputi : SBF generic map(
width_inl=>11, width_inr=>0, width_outl=>10, width_outr=>0,
lpm_signed=>BusIsUnsigned, round=>0, satur=>0)
port map (
xin=>A17W, yout=>SAOutputO);
-- Output - I/O assignment from Simulink Block \
Output1i : SBF generic map(
width_inl=>11, width_inr=>0, width_outl=>10, width_outr=>0,
lpm_signed=>BusIsUnsigned, round=>0, satur=>0)
port map (
xin=>A18W, yout=>SAOutput1O);
--Bus Formatting Simulink Block \AltBusi : SBF generic map(
width_inl=>34, width_inr=>0, width_outl=>32, width_outr=>0,
lpm_signed=>BusIsUnsigned, round=>0, satur=>0)
port map (
xin yout
=> A7W,
=> A0W(31 downto 0));
-- Delay Element - Simulink Block \Delayi : SDelay generic map (
LPM_WIDTH => 34, LPM_DELAY => 1, SequenceLength => 1, SequenceValue => 1)
=> A12W,
port map (dataa
clock => clock, => '1', => sclr, => A7W);
ena sclr result
-- Product Operator - Simulink Block \Producti : AltiMult generic map (
LPM_WIDTHA LPM_WIDTHB PIPELINE one_input
=> 11, => 9,
=> 0, => 0, => 1,
=> \
lpm lpm_hint cst_val
=> \
SequenceLength => 1, SequenceValue => 1, dspb_widthr
=> 20)
port map (
DATAA DATAB clock
=> A14W, => A5W, => '0', => '1', => '0', => A10W);
ena sclr result
-- Product Operator - Simulink Block \Product1i : AltiMult generic map (
LPM_WIDTHA LPM_WIDTHB PIPELINE one_input
=> 11, => 9,
=> 0, => 0, => 0,
lpm