fpga正交信号发生器课程设计(DOC)(5)

2019-01-27 11:42

lpm_hint cst_val

=> \

=> \

SequenceLength => 1, SequenceValue => 1, dspb_widthr

=> 20)

port map (

DATAA DATAB clock

=> A15W, => A6W, => '0', => '1', => '0', => A11W);

ena sclr result

-- Sum Operator - Simulink Block \ParallelAdderSubtractori : SAdderSub generic map (

lpm_width =>33, pipeline => 1, SequenceLength => 1, SequenceValue => 1, AddSubVal => AddAdd)

port map (

dataa datab clock

=> A0W, => A9W, => clock, => '1', => sclr, => A12W);

ena sclr result

-- Sum Operator - Simulink Block \ParallelAdderSubtractor1i : SAdderSub generic map (

lpm_width =>34, pipeline => 1,

SequenceLength => 1, SequenceValue => 1, AddSubVal => AddAdd)

port map (

dataa(32 downto 0) dataa(33) datab clock

=> A4W(32 downto 0),

=> A4W(32),

=> A7W, => clock, => '1', => sclr, => A13W);

ena sclr result

-- Look-up table - Simulink Block \LUTi : lpm_rom generic map (

LPM_WIDTH => 10, LPM_WIDTHAD => 10,

lpm_address_control => \lpm_outdata => \lpm_file => \port map (

address(9 downto 0) =>A16W(9 downto 0), inclock q

=>clock,

=> A14W(9 downto 0));

A14W(10) <= '0';

-- Look-up table - Simulink Block \LUT1i : lpm_rom

generic map (

LPM_WIDTH => 10, LPM_WIDTHAD => 10,

lpm_address_control => \

lpm_outdata => \lpm_file => \port map (

address(9 downto 0) =>A16W(9 downto 0), inclock q

=>clock,

=> A15W(9 downto 0));

A15W(10) <= '0';

-- Bus Conversion - Simulink Block \BusConversion1i : SRED generic map(

widthin=>32, widthout=>10, msb=>31, lsb=>22, round=>0,

lpm_signed=>BusIsUnsigned, satur=>0)

port map (

xin(31 downto 0) =>A13W(31 downto 0),

yout

=> A16W(9 downto 0));

-- Bus Conversion - Simulink Block \BusConversion2i : SRED generic map(

widthin=>20, widthout=>10, msb=>18, lsb=>9, round=>0,

lpm_signed=>BusIsUnsigned, satur=>0)

port map (

xin(19 downto 0) =>A10W(19 downto 0),

yout => A17W(9 downto 0));

-- Bus Conversion - Simulink Block \BusConversion3i : SRED generic map(

widthin=>20, widthout=>10, msb=>18, lsb=>9, round=>0,

lpm_signed=>BusIsUnsigned, satur=>0)

port map (

xin(19 downto 0) =>A11W(19 downto 0),

yout

=> A18W(9 downto 0));

clk<=clock;

end architecture aDspBuilder;


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