犯规功能模块的时序仿真图：
图 8.1
B组提前抢答，报警铃鸣叫示意
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3.5 总体电路的源程序以及仿真波形
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY qdq IS
PORT(A,B,C,D,tset,INI,EN,CLK:IN STD_LOGIC; tih:IN STD_LOGIC_VECTOR(5 DOWNTO 4); til:IN STD_LOGIC_VECTOR(3 DOWNTO 0); bell:OUT STD_LOGIC;
timeh:BUFFER STD_LOGIC_VECTOR(5 DOWNTO 4); timel:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0); obcd:OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); END;
ARCHITECTURE one OF qdq IS
SIGNAL G:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL R:STD_LOGIC; SIGNAL CLK1:STD_LOGIC; SIGNAL sel,outc:STD_LOGIC;
SIGNAL tah:STD_LOGIC_VECTOR(5 DOWNTO 4); SIGNAL tal:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN
LOCK:PROCESS(A,B,C,D,G,INI,CLK) BEGIN
IF(INI='1')THEN R<='0'; G<=\
ELSIF rising_edge(CLK)THEN
IF(A='1' OR G(3)='1')AND NOT (G(0)='1' OR G(1)='1' OR G(2)='1') THEN
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G(3)<='1'; END IF;
IF(B='1' OR G(2)='1')AND NOT (G(0)='1' OR G(1)='1' OR G(3)='1') THEN G(2)<='1'; END IF;
IF(C='1' OR G(1)='1')AND NOT (G(0)='1' OR G(2)='1' OR G(3)='1') THEN G(1)<='1'; END IF;
IF(D='1' OR G(0)='1')AND NOT (G(1)='1' OR G(2)='1' OR G(3)='1') THEN G(0)<='1'; END IF;
R<=A OR B OR C OR D; END IF; END PROCESS;
CB:PROCESS(CLK)
VARIABLE Q:STD_LOGIC_VECTOR(8 DOWNTO 0); BEGIN
IF CLK'EVENT AND CLK='1' THEN IF(Q=\ Q:=\ ELSE Q:=Q+1; END IF; END IF; CLK1<=Q(8); END PROCESS;
COUNT:PROCESS(tih,til,tset,timeh,timel,INI,EN,CLK1) BEGIN
IF rising_edge(CLK1) THEN
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IF tset='1' THEN tah<=tih; tal<=til; END IF; IF INI='1'THEN timeh<=tah; timel<=tal; ELSIF(EN='1')THEN timeh<=timeh; timel<=timel;
ELSIF(timeh=0 AND timel=0)THEN timeh<=timeh; timel<=timel; ELSIF(timel=0)THEN timel<=\ timeh<=timeh-1; ELSE
timel<=timel-1; timeh<=timeh; END IF; END IF; END PROCESS;
obcd<=\ \ \ \ \
sel<='1'WHEN(timeh=tah AND timel=tal)ELSE'0';
outc<='1'WHEN((timeh=0)AND(timel=0)AND(EN='0')AND(INI='0'))ELSE'0';
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bell<=((R AND sel)OR outc)AND CLK; END one;
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