8'd85,8'd86,8'd87,8'd88: count_end = M_2; 8'd89: count_end = M_1; 8'd90,8'd91: count_end = M_2; 8'd92,8'd93: count_end = M_6; 8'd94,8'd95,8'd96,8'd97: count_end = M_5; 8'd98,8'd99,8'd100: count_end = M_3; 8'd101,8'd102: count_end = M_5; 8'd103,8'd104,8'd105,8'd106: count_end = M_6; 8'd107,8'd108,8'd109,8'd110: count_end = M_6; 8'd111,8'd112: count_end = H_1; 8'd113,8'd114,8'd115,8'd116: count_end = M_5; 8'd117,8'd118,8'd119: count_end = M_3; 8'd120,8'd121: count_end = M_1; 8'd122,8'd123,8'd124,8'd125: count_end = M_2; 8'd126: count_end = M_1; 8'd127,8'd128: count_end = M_2; 8'd129,8'd130: count_end = M_3; 8'd131,8'd132,8'd133,8'd134: count_end = M_1; 8'd135,8'd136,8'd137: count_end = L_6; 8'd138,8'd139: count_end = M_5; 8'd140,8'd141,8'd142,8'd143: count_end = M_1; 8'd144,8'd145,8'd146,8'd147: count_end = M_1; default:count_end = 16'h0; endcase end end
endmodule
实验七 交通灯控制器
1、实验目的
学习交通灯控制器的设计，学习简单状态机的设计和硬件测试。 2、实验内容
本实验的内容是设计一个简易的交通灯控制器，要求能实现红黄绿三种灯的控制并通过数码管显示倒计时时间，整个设计在实验平台上实现。 3、实验原理
本实验的设计的交通灯控制器要求实现对A，B 两个方向的红，绿，黄三种灯的控制，并能实现时间显示的到计时。因此每个方向的灯可用一个状态机实现，状态的跳转顺序为灯-绿灯-黄灯-红灯（另一个的状态应为绿-黄-红-绿），同时设计一个计时器，来记录每种灯的道计时时间。最后将交通灯的状态信息输出，至数码管显示模块和交通灯模块。注意一个方向的绿灯时间应和另一个方向的红黄灯时间总和相等。 4、电路连接
（1）将EDA-MK-01模块跳线帽设置为SEG_a—SEG_dp和COM0—COM7端。 （2）引脚分配
PIN_23 -to clk PIN_4 -to rst_n PIN_34 -to lampa\\[0\\] PIN_37 -to lampa\\[1\\] PIN_35 -to lampa\\[2\\] PIN_108 -to lampb\\[0\\] PIN_117 -to lampb\\[1\\] PIN_39 -to lampb\\[2\\] PIN_74 -to seg\\[0\\] PIN_72 -to seg\\[1\\] PIN_69 -to seg\\[2\\] PIN_68 -to seg\\[3\\] PIN_67 -to seg\\[4\\] PIN_64 -to seg\\[5\\] PIN_63 -to seg\\[6\\] PIN_61 -to seg\\[7\\] PIN_86 -to dig\\[0\\] PIN_84 -to dig\\[1\\] PIN_82 -to dig\\[2\\] PIN_81 -to dig\\[3\\] PIN_80 -to dig\\[4\\] PIN_77 -to dig\\[5\\] PIN_76 -to dig\\[6\\] PIN_75 -to dig\\[7\\]
5、实验程序
（1） traffic.v
module traffic(clock,rst_n,clken,lampa,lampb,acount,bcount); input clock;
input rst_n; input clken; output [2:0] lampa; output [2:0] lampb; output [7:0] acount; output [7:0] bcount;
reg[2:0] lampa,lampb; reg[7:0] numa,numb; reg tempa,tempb; reg[2:0] StateA,StateB;
parameter ared =8'h30, //30秒 ayellow =8'h5, //5秒 agreen =8'h15, //15秒 bred =8'h20, //20秒 byellow =8'h5, //5秒 bgreen =8'h25; //25秒
assign acount=numa; assign bcount=numb;
//控制A方向的三种灯
always @(posedge clock or negedge rst_n) begin
if(!rst_n) begin StateA <= 3'h0; lampa <= 3'b011; tempa <= 1'b0; end
else if(clken) begin if(!tempa) begin tempa <= 1'b1; //防重进入标志 case(StateA) //控制亮灯的顺序 0: begin numa <= agreen; lampa <= 3'b011; StateA <= 1; end 1: begin numa <= ayellow; lampa <= 3'b101; StateA <= 2; end 2: begin numa <= ared; lampa <= 3'b110; StateA <= 0; end
default: endcase end else
lampa <= 3'b110;
begin //倒计时 if(numa>1) if(numa[3:0]==0) begin numa[3:0]<=4'h9; numa[7:4]<=numa[7:4]-4'h1; end else numa[3:0]<=numa[3:0]-4'h1; if (numa==2) tempa<=1'b0; end end end
//控制B方向的三种灯
always @(posedge clock or negedge rst_n) begin
if(!rst_n) begin lampb<=3'b110; StateB<=3'h0; tempb<=1'b0; end
else if (clken) begin
if(!tempb) begin tempb<=1'b1; //防重进入标志 case (StateB) //控制亮灯的顺序 0: begin numb<=bred; lampb<=3'b110; StateB<=1; end 1: begin numb<=bgreen; lampb<=3'b011; StateB<=2; end 2: begin numb<=byellow; lampb<=3'b101; StateB<=0; end default: lampb<=3'b110; endcase end else begin //倒计时
if(numb>1) if(numb[3:0]==0) begin numb[3:0]<=4'h9; numb[7:4]<=numb[7:4]-4'h1; end else numb[3:0]<=numb[3:0]-4'h1; if(numb==2) tempb <= 1'b0; end end end
endmodule
（2） traffic_test.v
module traffic_test(clock,clken,rst_n,acount,bcount,seg,dig);
input clock; input rst_n; output clken;
input [7:0] acount; input [7:0] bcount; output [7:0] seg; output [7:0] dig; //I/O寄存器 reg[7:0]seg; reg[7:0]dig;
//系统时钟(50MHz)
//内部寄存器 reg[25:0]clk_cnt; reg[16:0]count; reg[1:0] cnt; reg[3:0]disp_dat; wire div_clk;
//产生1Hz时钟使能信号 always @(posedge clock) begin if(clken) clk_cnt <= 26'h0; else clk_cnt <= clk_cnt + 26'h1; end
assign clken = (clk_cnt >= 26'd49999999);