盐城工学院本科生毕业设计说明书（2007）
rst => rst,
clk_out => clk_T); u2 : double3and6 port map (cp => clk_T, dir => dir, ex => ex,
mode => mode, outA => outA, outB => outB, end rt1_top_level;
outC => outC); 27
基于CPLD的多功能脉冲分配器系统的设计
附录2 分频程序清单 library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; entity divider is
port(cp: in std_logic;
a1,a2,a3: in std_logic; rst: in std_logic;
clk_out: out std_logic); end divider;
architecture a of divider is
signal count:std_logic_vector(1 downto 0); signal mode:std_logic_vector(2 downto 0); signal clk_temp:std_logic;
signal cnt1,cnt2:integer range 0 to 2; signal cnt3,cnt4:integer range 0 to 4; signal cnt5,cnt6:integer range 0 to 6;
signal clk1,clk2,clk3,clk4,clk5,clk6:std_logic;
signal clk_out1,clk_out2,clk_out3,clk_out4,clk_outT,clk_outTT:std_logic; begin
mode <= a3&a2&a1;
process(cp, count, mode, clk_temp) begin
if(cp'event and cp = '1') then if mode = \ if (count = \ count <= (others=>'0'); clk_temp <= not clk_temp; end if; end if;
if mode = \ if (count = \ count <= (others=>'0'); clk_temp <= not clk_temp; else
count <= count + 1; end if; end if;
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盐城工学院本科生毕业设计说明书（2007）
if mode = \ if (count = \ count <= (others=>'0'); clk_temp <= not clk_temp; else
count <= count + 1; end if; end if;
if mode = \ if (count = \ count <= (others=>'0'); clk_temp <= not clk_temp; else
count <= count + 1; end if; end if; end if; end process;
clk_out1 <= clk_temp;
process(cp, mode,clk1,cnt1) begin
if(cp'event and cp = '1') then if mode = \ if(cnt1 < 2) then cnt1 <= cnt1 + 1; else
cnt1 <= 0; end if;
if(cnt1 < 1) then clk1 <= '1'; else
clk1 <= '0'; end if; end if; end if; end process;
process(cp, mode,clk2,cnt2) begin
if(cp'event and cp = '0') then if mode = \
29
基于CPLD的多功能脉冲分配器系统的设计
if(cnt2 < 2) then cnt2 <= cnt2 + 1; else
cnt2 <= 0; end if;
if(cnt2 < 1) then clk2 <= '1'; else
clk2 <= '0'; end if; end if; end if; end process;
clk_out2 <= clk1 or clk2; process(cp, mode,clk3,cnt3) begin
if(cp'event and cp = '1') then if mode = \ if(cnt3 < 4) then cnt3 <= cnt3 + 1; else
cnt3 <= 0; end if;
if(cnt3 < 2) then clk3 <= '1'; else
clk3 <= '0'; end if; end if; end if; end process;
process(cp, mode,clk4,cnt4) begin
if(cp'event and cp = '0') then if mode = \ if(cnt4 < 4) then cnt4 <= cnt4 + 1; else
cnt4 <= 0; end if;
30
盐城工学院本科生毕业设计说明书（2007）
if(cnt4 < 2) then clk4 <= '1'; else
clk4 <= '0'; end if; end if; end if; end process;
clk_out3 <= clk3 or clk4; process(cp, mode,clk5,cnt5) begin
if(cp'event and cp = '1') then if mode = \ if(cnt5 < 6) then cnt5 <= cnt5 + 1; else
cnt5 <= 0; end if;
if(cnt5 < 3) then clk5 <= '1'; else
clk5 <= '0'; end if; end if; end if; end process;
process(cp, mode,clk6,cnt6) begin
if(cp'event and cp = '0') then if mode = \ if(cnt6 < 6) then cnt6 <= cnt6 + 1; else
cnt6 <= 0; end if;
if(cnt6 < 3) then clk6 <= '1'; else
clk6 <= '0'; end if;
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