基于VHDL的编码器和译码器的设计 第18页 共20页
1.8线-3线优先编码器的VHDL程序代码： --程序名：priority.vhd library ieee;
use ieee.std_logic_1164.all; entity priority is
port(i:in bit_vector(7 downto 0); a:out bit_vector(2 downto 0); gs:out bit); end priority;
architecture a of priority is begin
process(i) begin
gs<='1'; a<=\ if i(7)='1'then a<=\ elsif i(6)='1'then a<=\ elsif i(5)='1'then a<=\ elsif i(4)='1'then a<=\ elsif i(3)='1'then a<=\ elsif i(2)='1'then a<=\ elsif i(1)='1'then a<=\ elsif i(0)='1'then
基于VHDL的编码器和译码器的设计 第19页 共20页
a<=\ else gs<='0'; end if; end process; end a;
2.3线-8线译码器的VHDL程序代码： library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity decode_38 is
Port (datain : in std_logic_vector(2 downto 0);
cs : out std_logic;
dataout: out std_logic_vector(7 downto 0));
end decode_38;
architecture Behavioral of decode_38 is begin cs<='1'; process(datain) begin
case datain is
when \ when \ when \ when \ when \ when \ when \ when \
基于VHDL的编码器和译码器的设计 第20页 共20页
when others=>dataout<=\ end case; end process; end Behavioral;
3.2线-4线译码器的VHDL程序代码： --2线-4线译码器的顺序条件语句描述 --程序名：decode_24.vhd library ieee;
use ieee.std_logic_1164.all; entity decode_24 is
port(i:in std_logic_vector(1 downto 0); o:out std_logic_vector(3 downto 0)); end decode_24;
architecture a of decode_24 is begin process(i) begin case i is
when \ when \ when \ when \ when others =>o<=\ end case; end process; end a;