Verilog实现智能电梯控制器(7)

带液晶显示驱动的智能电梯控制器

);

//////////////////////// Clock Input ////////////////////////

input open_enable,stop_enable,up_enable,down_enable,close_enable; input CLOCK_50; // 50 MHz input KEY;

//////////////////// LCD Module 16X2 //////////////////////////// inout [7:0] LCD_DATA; // LCD Data bus 8 bits output LCD_ON; // LCD Power ON/OFF output LCD_BLON; // LCD Back Light ON/OFF output LCD_RW; // LCD Read/Write Select, 0 = Write, 1 = Read output LCD_EN; // LCD Enable output LCD_RS; // LCD Command/Data Select, 0 = Command, 1 = Data

// LCD ON

assign LCD_ON = 1'b1; assign LCD_BLON = 1'b1; reg [31:0] Cont; wire DLY_RST;

always@(posedge CLOCK_50 or negedge KEY) begin if(!KEY) Cont <= 0; else Cont <= Cont+1; end

Reset_Delay r0 ( .iCLK(CLOCK_50),.oRESET(DLY_RST) ); LCD_TEST u5 ( // Host Side .iCLK(CLOCK_50), .iRST_N(DLY_RST), .iup_enable(up_enable), .idown_enable(down_enable), .iclose_enable(close_enable), .iopen_enable(open_enable), .istop_enable(stop_enable), // LCD Side .LCD_DATA(LCD_DATA), .LCD_RW(LCD_RW), .LCD_EN(LCD_EN), .LCD_RS(LCD_RS) );

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带液晶显示驱动的智能电梯控制器

endmodule

5.7 LCD控制模块

module LCD_Controller ( // Host Side iDATA,iRS, iStart,oDone, iCLK,iRST_N, // LCD Interface LCD_DATA, LCD_RW, LCD_EN, LCD_RS ); // CLK

parameterCLK_Divide = 16;

// Host Side input [7:0] iDATA; input iRS,iStart; input iCLK,iRST_N; output reg oDone; // LCD Interface

output [7:0] LCD_DATA; output reg LCD_EN; output LCD_RW; output LCD_RS; // Internal Register reg [4:0] Cont; reg [1:0] ST; reg preStart,mStart;

/////////////////////////////////////////////

// Only write to LCD, bypass iRS to LCD_RS assign LCD_DATA = iDATA; assign LCD_RW = 1'b0; assign LCD_RS = iRS; /////////////////////////////////////////////

always@(posedge iCLK or negedge iRST_N) begin if(!iRST_N) begin oDone <= 1'b0;

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带液晶显示驱动的智能电梯控制器

LCD_EN <= 1'b0; preStart<= 1'b0; mStart <= 1'b0; Cont <= 0; ST <= 0; end else begin ////// Input Start Detect /////// preStart<= iStart; if({preStart,iStart}==2'b01) begin mStart <= 1'b1; oDone <= 1'b0; end ////////////////////////////////// if(mStart) begin case(ST) 0: ST <= 1; // Wait Setup 1: begin LCD_EN <= 1'b1; ST <= 2; end 2: begin if(Cont

endmodule

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带液晶显示驱动的智能电梯控制器

5.8 LCD显示模块

module LCD_TEST ( // Host Side iCLK,iRST_N,iopen_enable,iup_enable, idown_enable,iclose_enable,istop_enable, // LCD Side LCD_DATA,LCD_RW,LCD_EN,LCD_RS ); // Host Side input iCLK,iRST_N;

input idown_enable,iclose_enable,istop_enable,iopen_enable,iup_enable; // LCD Side

output [7:0] LCD_DATA; output LCD_RW,LCD_EN,LCD_RS; // Internal Wires/Registers reg [5:0] LUT_INDEX; reg [8:0] LUT_DATA; reg [5:0] mLCD_ST; reg [17:0] mDLY; reg mLCD_Start; reg [7:0] mLCD_DATA; reg mLCD_RS; reg ok; wire mLCD_Done;

parameterLCD_INTIAL = 0; parameterLCD_LINE1 = 5;

parameterLCD_CH_LINE = LCD_LINE1+16; parameterLCD_LINE2 = LCD_LINE1+16+1; parameterLUT_SIZE = LCD_LINE1+32+1;

always@(posedge iCLK or negedge iRST_N) begin if(!iRST_N) begin LUT_INDEX <= 0; mLCD_ST <= 0; mDLY <= 0; mLCD_Start <= 0; mLCD_DATA <= 0; mLCD_RS <= 0; end else begin if(LUT_INDEX

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带液晶显示驱动的智能电梯控制器

begin case(mLCD_ST) 0: begin mLCD_DATA <= LUT_DATA[7:0]; mLCD_RS <= LUT_DATA[8]; mLCD_Start <= 1; mLCD_ST <= 1; end 1: begin if(mLCD_Done) begin mLCD_Start <= 0; mLCD_ST <= 2; end end 2: begin if(mDLY<18'h00008) mDLY <= mDLY+1; else begin mDLY <= 0; mLCD_ST <= 3; end end 3: begin LUT_INDEX <= LUT_INDEX+1; mLCD_ST <= 0; end endcase end else //如果已发完第一遍数据，就刷新 begin LUT_INDEX <= 0; end end end

always begin

if(iopen_enable)//如果LCD仲裁器的“开门使能”有效就执行：

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