南昌航空大学学士学位论文
.key_up(Key_Out[4]), .key_down(Key_Out[3]), .key_stop(Key_Out[0]), .row_data(row_data) ); displ_led u5( .clk(CLK), .rst(RSTn), .row_data(row_data), .data(data), .rclk(rclk), .sclk(sclk), .ser(ser), .AB(AB), .s_clk(s_clk), .isdone(isdone) ); rtc_smg u6( .CLK(CLK), .RSTn(RSTn), .scan(scan), .smg_data(smg_data), .rst(rst), .sclk(sclk_rtc), .SIO(SIO) ); Endmodule
串口接收模块例化模块 rx_tx_interface.v
module rx_tx_interface (
input CLK, input RSTn, input RX_Pin_In, output [15:0] write_data, input isdone );
/******************************/ wire [7:0]FIFO_Read_Data; wire Empty_Sig; rx_interface U1 ( .CLK( CLK ), .RSTn( RSTn ), .RX_Pin_In( RX_Pin_In ), // input - from top .Read_Req_Sig( Read_Req_Sig ), // input - from U2 .FIFO_Read_Data( FIFO_Read_Data ), // output - to U2 .Empty_Sig( Empty_Sig ) // output - to U2 ); /******************************/
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南昌航空大学学士学位论文
wire Read_Req_Sig; wire [7:0]FIFO_Write_Data; inter_control_module U2 ( .CLK( CLK ), .RSTn( RSTn ), .Empty_Sig( Empty_Sig ), // input - from U1 .FIFO_Read_Data( FIFO_Read_Data ), // input - from U1 .Read_Req_Sig( Read_Req_Sig ), // output - to U1 .FIFO_Write_Data( FIFO_Write_Data )// output - ); /******************************/ displ U3( .CLK(CLK), .RSTn(RSTn), .FIFO_Write_Data( FIFO_Write_Data ), .write_data(write_data), .isdone(isdone) ); /******************************/
Endmodule
串口接收检测模块 detect_module.v
module detect_module (
CLK, RSTn, RX_Pin_In, H2L_Sig );
input CLK; input RSTn; input RX_Pin_In; output H2L_Sig; /******************************/ reg H2L_F1; reg H2L_F2; always @ ( posedge CLK or negedge RSTn ) if( !RSTn ) begin H2L_F1 <= 1'b1; H2L_F2 <= 1'b1; end else begin H2L_F1 <= RX_Pin_In; H2L_F2 <= H2L_F1; end
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南昌航空大学学士学位论文
/***************************************/ assign H2L_Sig = H2L_F2 & !H2L_F1; /***************************************/
Endmodule
波特率发生模块 rx_bps_module.v
module rx_bps_module (
CLK, RSTn, Count_Sig, BPS_CLK );
input CLK; input RSTn; input Count_Sig; output BPS_CLK; /***************************/ reg [11:0]Count_BPS; always @ ( posedge CLK or negedge RSTn ) if( !RSTn ) Count_BPS <= 12'd0; else if( Count_BPS == 12'd2082 ) Count_BPS <= 12'd0; else if( Count_Sig ) Count_BPS <= Count_BPS + 1'b1; else Count_BPS <= 12'd0; /********************************/
assign BPS_CLK = ( Count_BPS == 12'd1041 ) ? 1'b1 : 1'b0;
/*********************************/
Endmodule
串口接收控制模块 rx_control_module.v
module rx_control_module (
CLK, RSTn, H2L_Sig, RX_Pin_In, BPS_CLK, RX_En_Sig, Count_Sig, RX_Data, RX_Done_Sig );
input CLK; input RSTn;
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南昌航空大学学士学位论文
input H2L_Sig; input RX_En_Sig; input RX_Pin_In; input BPS_CLK; output Count_Sig; output [7:0]RX_Data; output RX_Done_Sig; /********************************************************/ reg [3:0]i; reg [7:0]rData; reg isCount; reg isDone; always @ ( posedge CLK or negedge RSTn ) if( !RSTn ) begin i <= 4'd0; rData <= 8'd0; isCount <= 1'b0; isDone <= 1'b0; end else if( RX_En_Sig ) case ( i ) 4'd0 : if( H2L_Sig ) begin i <= i + 1'b1; isCount <= 1'b1; end 4'd1 : if( BPS_CLK ) begin i <= i + 1'b1; end 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9 : if( BPS_CLK ) begin i <= i + 1'b1; rData[ i - 2 ] <= RX_Pin_In; end 4'd10 : if( BPS_CLK ) begin i <= i + 1'b1; end 4'd11 : if( BPS_CLK ) begin i <= i + 1'b1; end 4'd12 : begin i <= i + 1'b1; isDone <= 1'b1; isCount <= 1'b0; end 4'd13 : begin i <= 1'b0; isDone <= 1'b0; end endcase
/********************************************************/ assign Count_Sig = isCount; assign RX_Data = rData; assign RX_Done_Sig = isDone;
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南昌航空大学学士学位论文
/*********************************************************/
Endmodule
串口接收模块顶层控制模块 rx_top_control_module.v module rx_top_control_module (
input CLK, input RSTn, input RX_Done_Sig, input [7:0]RX_Data, output RX_En_Sig, input Full_Sig, output Write_Req_Sig, output [7:0]FIFO_Write_Data );
/*************************************/ reg [1:0]i; reg isWrite; reg isRX; always @ ( posedge CLK or negedge RSTn ) if( !RSTn ) begin i <= 2'd0; isWrite <= 1'b0; isRX <= 1'b0; end else case( i ) 0: if( RX_Done_Sig ) begin isRX <= 1'b0; i <= i + 1'b1; end else isRX <= 1'b1; 1: if( !Full_Sig ) i <= i + 1'b1; 2: begin isWrite <= 1'b1; i <= i + 1'b1; end 3: begin isWrite <= 1'b0; i <= 2'd0; end endcase
/*************************************/ assign RX_En_Sig = isRX; assign Write_Req_Sig = isWrite; assign FIFO_Write_Data = RX_Data; /*************************************/
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