endmodule
10、奇偶检验位生成器
module parity(even_bit,odd_bit,input_bus); output even_bit,odd_bit; input[7:0] input_bus;
assign odd_bit = ^ input_bus; //产生奇校验位 assign even_bit = ~odd_bit; //产生偶校验位 endmodule
11、三态输出驱动器
①module trist(out,in,enable); output out; input in,enable;
assign out=enable?in:’bz; endmodule
②module trist(out,in,enable); output out; input in,enable;
bufifl mybufl(out,in,enable); endmodule
12、8位移位寄存器
module shifter(din,clk,clr,dout); input din,clk,clr; output[7:0] dout; reg[7:0] dout;
always @(posedge clk) begin
if (clr) dout<= 8'b0; else
begin
dout <= dout << 1; dout[0] <= din; end end endmodule 13、四位计数器
module counter(Q,clock,clear); output[3:0]Q; input clock,clear; reg[3:0]Q;
always@(posedge clear or negedge clock) begin if(clear)
Q<=4’d0; else
//同步清0，高电平有效 //输出信号左移一位
//输入信号补充到输出信号的最低位 Q<=Q+1;
end
endmodule
5）程序设计题：
1.五人表决器的设计 module vote5(a,b,c,d,e,f); input a,b,c,d,e; output f; reg f;
reg[2:0] count1; initial count1=0; always@(a,b,c,d,e) begin
count1<=a+b+c+d+e; f=count1<3?0:1; end
endmodule
2.分频器的设计 module adder(clk,z); output z; reg q; reg z;
always@(posedge clk) begin if(q%9==0) z<=q; else q=q+1; end
endmodule
module counter9(clk,datein,z); output z; input clk; input datein; reg z;
reg[3:0] q;
always@(posedge clk) begin q<=q+1;
if (q==4'b1001) begin
q<=4'b0000; z<=datein; end end
endmodule
3.7段数码管的译码器设计 module SEG7_LUT ( input [3:0] iDIG, output reg [6:0] oSEG );
always@(iDIG) begin
case(iDIG)
4'h1: oSEG = 7'b1111001; // ---t---- 4'h2: oSEG = 7'b0100100; // | | 4'h3: oSEG = 7'b0110000; // lt rt 4'h4: oSEG = 7'b0011001; // | | 4'h5: oSEG = 7'b0010010; // ---m---- 4'h6: oSEG = 7'b0000010; // | | 4'h7: oSEG = 7'b1111000; // lb rb 4'h8: oSEG = 7'b0000000; // | | 4'h9: oSEG = 7'b0011000; // ---b---- 4'ha: oSEG = 7'b0001000; 4'hb: oSEG = 7'b0000011; 4'hc: oSEG = 7'b1000110; 4'hd: oSEG = 7'b0100001; 4'he: oSEG = 7'b0000110; 4'hf: oSEG = 7'b0001110; default: oSEG = 7'b1000000; endcase end endmodule
4.计数器的设计
module counter(input bn, output reg[7:0] segcode, output [3:0] an );
reg[3:0] count; assign an=4'b0111; initial begin count=0; end
always @(posedge bn) count<=count+1; always @(count) case(count)
0:segcode=8'b11000000;//0
1:segcode=8'b11111001;//1 2:segcode=8'b10100100;//2 3:segcode=8'b10110000;//3 4:segcode=8'b10011001;//4 5:segcode=8'b10010010;//5 6:segcode=8'b10000010;//6 7:segcode=8'b11111000;//7 8:segcode=8'b10000000;//8 9:segcode=8'b10010000;//9 'ha:segcode=8'b10001000;//a 'hb:segcode=8'b10000011;//b 'hc:segcode=8'b11000110;//c 'hd:segcode=8'b10100001;//d 'he:segcode=8'b10000110;//e 'hf:segcode=8'b10001110;//f default:segcode=8'b11111111; endcase endmodule 5.流水灯的设计 module ledflash( output [7:0] ld, input clk ); reg clk1s; reg[7:0] tmp; reg[31:0] count; assign ld=tmp; initial begin clk1s=0;
tmp=8'b00000001; count=0; end
always@(posedge clk) begin
count<=count+1;
if (count==25000000) begin count<=0; clk1s<=~clk1s; end end
always@(posedge clk1s) begin
if (clk1s==1)
tmp={tmp[6:0],tmp[7]}; end
endmodule
6.移位寄存器（略）
7.根据状态转移图写Verilog模块(4状态模型如下) Module fsm(clock,reset,a,k2,k1); input clock,reset,a; output k2,k1; output[1 :0]state ; reg k2,k1 ; reg[1 :0]state ;
paremeter Idle=2’b00 ;
Start=2’b01 ; Stop=2’b10 ;
Clear=2’b11 ; always@(posedge clock) if( !reset) begin
state<=Idle ; k2<=0 ; k1<=0 ; end else
case(state)
Idle :if(a) begin
state<=Start ; K1<=0 ; end Else begin
state<=Idle ; k2<=0 ; k1<=0 ; end
Start :if( !a)state<=Stop ; else state<=Start ; end Stop :if(a)begin
state<=Clear ; k2<=1 ; end else begin
start<=Stop ; k2<=0 ;
k1<=0 ; end
Clear :if( !a)begin
State<=Idle ; K2<=0 ; K1<=1 ; End Else begin
State<=Clear : K2<=0 ; K1<=1 ; End
Default :state<=2’bxx ; Endcase
Endmodule
8.运算器的设计（加、减、乘、按位与等） module jsq(a,b,c,out); input[7:0]a,b; input[1:0]c; otput[15:0]out; reg [15:0]out
reg[7:0]out1,out2; always@(a,b,c,out) case(c)
2'b00:out=a+b; 2'b01:out=a-b; 2'b10:out=a*b; 2'b11: begin out1=a/b; out2=a%b;
out={out1,out2}; end default:; endcase endmodule