k1<=0 ; end
Clear :if( !a)begin
State<=Idle ; K2<=0 ; K1<=1 ; End Else begin
State<=Clear : K2<=0 ; K1<=1 ; End
Default :state<=2’bxx ; Endcase
Endmodule
8.运算器的设计（加、减、乘、按位与等） module jsq(a,b,c,out); input[7:0]a,b; input[1:0]c; otput[15:0]out; reg [15:0]out
reg[7:0]out1,out2; always@(a,b,c,out) case(c)
2'b00:out=a+b; 2'b01:out=a-b; 2'b10:out=a*b; 2'b11: begin out1=a/b; out2=a%b;
out={out1,out2}; end default:; endcase endmodule