my_c[i]=my_a[i]&my_b[i]; endtask
endmodule 代码7:83编码器 module code_83(din,dout); input[7:0] din; output[2:0] dout;
function[2:0] code; input[7:0] din; casex (din)
8'b1xxx_xxxx : code = 3'h7; 8'b01xx_xxxx : code = 3'h6; 8'b001x_xxxx : code = 3'h5; 8'b0001_xxxx : code = 3'h4; 8'b0000_1xxx : code = 3'h3; 8'b0000_01xx : code = 3'h2; 8'b0000_001x : code = 3'h1; 8'b0000_000x : code = 3'h0; default: code = 3'hx; endcase endfunction
assign dout = code(din) ; endmodule
代码8:函数实现非波拉切序列
module funct(clk,n,result,reset); output[31:0] result; input[3:0] n; input reset,clk; reg[31:0] result;
always @(posedge clk) begin
if(!reset) result<=0; else begin
result <= 2 * factorial(n); end end
function[31:0] factorial; input[3:0] opa; reg[3:0] i; begin
factorial = opa ? 1 : 0; for(i=2;i<=opa;i=i+1) factorial = i* factorial; end endfunction
代码9:3过程实现101检测,fsm module TEST101(CLOCK_50,HEX0,KEY); input CLOCK_50; input[1:0] KEY; output[6:0] HEX0; reg[1:0] state,next_state; reg[3:0] count;
reg[32:0] temp=33'b000101010101001010101; parameter s0=2'b00,s1=2'b01,s2=2'b11,s3=2'b10; div_clock_1hz(CLOCK_50,CLK_1); de_16to7seg(count,HEX0);
always@(posedge CLK_1 or negedge KEY[0]) begin
if(!KEY[0]) temp<=11'b01001010101; else temp<=temp>>1; end
always@(posedge CLK_1 or negedge KEY[0])
begin
if(!KEY[0]) state<=s0; else state<=next_state; end
always@(state or temp[0]) begin case(state)
s0:if(temp[0])next_state<=s1; else next_state<=s0; s1:if(temp[0])next_state<=s1; else next_state<=s2; s2:if(temp[0])next_state<=s3; else next_state<=s0; s3:if(temp[0])next_state<=s1; else next_state<=s2; default:next_state<=s0; endcase end
always@(state) begin case(state)
s3:count<=count+1; endcase end
endmodule
代码10: 三种速度的hello显示
module test100(KEY,CLOCK_50,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7,LEDR); input[1:0] KEY; input CLOCK_50; output[3:0] LEDR;
output[6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7; reg[55:0]
temp=56'B1111111_1111111_11111111_0001001_0000110_1000111_1000111_1000000;
reg[1:0] j;
assign LEDR={2'B00,j}; clock_1hz(CLOCK_50,CLK_1);
clock_025hz(CLOCK_50,CLK_025); clock_4hz(CLOCK_50,CLK_4);
assign clock=(j==0)?CLK_1:((j==2)?CLK_4:CLK_025);
assign {HEX7,HEX6,HEX5,HEX4,HEX3,HEX2,HEX1,HEX0}=temp; always@( KEY[0] or KEY[1]) begin
if(!KEY[0]) j=1;else j=0; if(!KEY[1]) j=2; else j=0; end
always@(posedge clock) begin
temp={temp,temp[55:49]}; end endmodule
module clock_1hz(clock_in,clock_out); input clock_in; output reg clock_out; integer i;
always@(posedge clock_in) begin
if(i==25000000) begin clock_out<=~clock_out; i<=0;end else i<=i+1; end
endmodule
module clock_025hz(clock_in,clock_out); input clock_in; output reg clock_out; integer i;
always@(posedge clock_in) begin
if(i==6250000) begin clock_out<=~clock_out; i<=0;end else i<=i+1;
end
endmodule
module clock_4hz(clock_in,clock_out); input clock_in; output reg clock_out; integer i;
always@(posedge clock_in) begin
if(i==100000000) begin clock_out<=~clock_out; i<=0;end else i<=i+1; end
endmodule
代码11:函数实现hello显示
module test002(SW,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7); input[17:0] SW;
output reg[6:0] HEX0,HEX1,HEX2,HEX3,HEX4; output[6:0] HEX5,HEX6,HEX7;
assign {HEX5,HEX6,HEX7}=21'B1111111_1111111_11111111; always@(SW) begin
case(SW[17:15])
3'b000:{HEX0,HEX1,HEX2,HEX3,HEX4}={decout(SW[2:0]),decout(SW[5:3]),decout(SW[8:6]),decout(SW[11:9]),decout(SW[14:12])};
3'b001:{HEX0,HEX1,HEX2,HEX3,HEX4}={decout(SW[5:3]),decout(SW[8:6]),decout(SW[11:9]),decout(SW[14:12]),decout(SW[2:0])};
3'b010:{HEX0,HEX1,HEX2,HEX3,HEX4}={decout(SW[8:6]),decout(SW[11:9]),decout(SW[14:12]),decout(SW[2:0]),decout(SW[5:3])};