if(temp[11:8]==4'b0) begin
temp[11:8]<=4'd9; end
else temp[11:8]<=temp[11:8]-1'b1; end
else temp[7:4]<=temp[7:4]-1'b1; end
else temp[3:0]<=temp[3:0]-1'b1; end end endmodule
module div_clock_1hz(clock_in,clock_out,clr);//1hz分频 input clock_in,clr; output reg clock_out; integer i;
always@(posedge clock_in or posedge clr) begin if(clr) i<=0;
else if(i==25000000) begin clock_out<=~clock_out; i<=0;end else i<=i+1; end
endmodule
代码14:时钟控制下的hello循环显示
module test003_sx_1(CLOCK_50,HEX7,HEX6,HEX5,HEX4,HEX3,HEX2,HEX1,HEX0,KEY); input CLOCK_50; input[1:0] KEY;
output[6:0] HEX7,HEX6,HEX5,HEX4,HEX3,HEX2,HEX1,HEX0; reg[31:0] temp;
div_clock_1hz(CLOCK_50,clock_1,KEY[0]); de_16to7seg(temp[31:28],HEX7); de_16to7seg(temp[27:24],HEX6); de_16to7seg(temp[23:20],HEX5);
de_16to7seg(temp[19:16],HEX4); de_16to7seg(temp[15:12],HEX3); de_16to7seg(temp[11:8],HEX2); de_16to7seg(temp[7:4],HEX1); de_16to7seg(temp[3:0],HEX0);
always@(posedge clock_1 or negedge KEY[0]) begin
if(!KEY[0]) temp<=32'H44401223; else begin
temp<={temp,temp[31:28]}; end end endmodule
代码15:模60计数,bcd码方式,此题目为时分秒计数,只考虑秒计时, module test004(CLOCK_50,KEY,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5); input CLOCK_50; input[1:0] KEY;
output[6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5; reg[5:0] sec,min,hour;
div_clock_1hz (CLOCK_50,clock_1); de_16to7seg a1((hour/10),HEX5); de_16to7seg a2(hour,HEX4); de_16to7seg a3((min/10),HEX3); de_16to7seg a4(min,HEX2); de_16to7seg a5((sec/10),HEX1); de_16to7seg a6(sec,HEX0); always@(posedge clock_1 ) begin
if(sec==6'd59) begin sec<=6'd0; if(min==6'd59) begin
if(hour==6'd59) hour<=6'd0; else hour<=hour+1'b1; end
else min<=min+1'b1; end
else sec<=sec+1'b1; end endmodule