3'b011:{HEX0,HEX1,HEX2,HEX3,HEX4}={decout(SW[11:9]),decout(SW[14:12]),decout(SW[2:0]),decout(SW[5:3]),decout(SW[8:6])};
3'b100:{HEX0,HEX1,HEX2,HEX3,HEX4}={decout(SW[14:12]),decout(SW[2:0]),decout(SW[5:3]),decout(SW[8:6]),decout(SW[11:9])};
default:{HEX4,HEX3,HEX2,HEX1,HEX0}=35'B1111111_1111111_1111111_1111111_1111111;
endcase end
function[6:0] decout; input[2:0] ina; case(ina)
3'b000:decout=7'b0001001; 3'b001:decout=7'b0000110; 3'b010:decout=7'b1000111; 3'b011:decout=7'b1000000; 3'b100:decout=7'b1111111; default:decout=7'b0001111; endcase endfunction endmodule
代码12:sw输入两个16位数,在2组7段管上显示 (1) 两个数在特定位置上显示
module test_sx_0010(KEY,SW,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7); input[15:0] SW; input[1:0] KEY;
output[6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7; reg[31:0] temp; reg state1;
de_16to7seg A1(temp[31:28],HEX7); de_16to7seg A2(temp[27:24],HEX6);
de_16to7seg A3(temp[23:20],HEX5); de_16to7seg A4(temp[19:16],HEX4); de_16to7seg A5(temp[15:12],HEX3); de_16to7seg A6(temp[11:8],HEX2); de_16to7seg A7(temp[7:4],HEX1); de_16to7seg A8(temp[3:0],HEX0);
always@(negedge KEY[1] or negedge KEY[0]) begin
if(!KEY[0]) temp<=32'B0; else if(!state1) temp[31:16]<=SW; else temp[15:0]<=SW; end
always@(negedge KEY[1] or negedge KEY[0]) begin
if(!KEY[0]) state1<=0; else state1<=state1+1'b1; end endmodule (2)移位方式显示
module test_sx_001(KEY,SW,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7); input[15:0] SW; input[1:0] KEY;
output[6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7; reg[31:0] temp; //reg state1;
de_16to7seg A1(temp[31:28],HEX7); de_16to7seg A2(temp[27:24],HEX6); de_16to7seg A3(temp[23:20],HEX5); de_16to7seg A4(temp[19:16],HEX4); de_16to7seg A5(temp[15:12],HEX3); de_16to7seg A6(temp[11:8],HEX2);
de_16to7seg A7(temp[7:4],HEX1); de_16to7seg A8(temp[3:0],HEX0);
always@(negedge KEY[1] or negedge KEY[0]) begin
if(!KEY[0]) temp<=32'B0; else temp<={temp,SW}; end endmodule 7段管译码模块
module de_16to7seg(ina,decodeout); input[3:0] ina;
output reg[6:0] decodeout; always@(ina) case(ina)
4'b0000:decodeout=7'b1000000;//0 4'b0001:decodeout=7'b1111001; 4'b0010:decodeout=7'b0100100; 4'b0011:decodeout=7'b0110000; 4'b0100:decodeout=7'b0011001; 4'b0101:decodeout=7'b0010010; 4'b0110:decodeout=7'b0000010; 4'b0111:decodeout=7'b1111000; 4'b1000:decodeout=7'b0000000; 4'b1001:decodeout=7'b0010000;//9 4'b1010:decodeout=7'b0001000;//a 4'b1011:decodeout=7'b0000011;//b 4'b1100:decodeout=7'b1000110;//c 4'b1101:decodeout=7'b0100001;//d 4'b1110:decodeout=7'b0000110;//e 4'b1111:decodeout=7'b0001110;//f default:decodeout=7'b1111111; endcase
endmodule
代码13:999计数
module test_sx_002_1(CLOCK_50,HEX0,HEX2,HEX1,HEX3,HEX4,HEX5,HEX6,HEX7,SW);//二进制计数器
input CLOCK_50; input[1:0] SW;
output[6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7; reg[9:0] temp;
assign {HEX3,HEX4,HEX5,HEX6,HEX7}=35'HFFFFFFFFF; div_clock_1hz c1(CLOCK_50,clock_1,SW[0]); de_16to7seg d1((temp/100),HEX2); de_16to7seg d2((temp/10),HEX1); de_16to7seg d3(temp,HEX0);
always@(posedge clock_1 or posedge SW[0]) begin
if(SW[0]) temp<=10'b0; else if(SW[1]) begin
if(temp==10'd999) temp<=10'd0; else temp<=temp+1'b1; end else begin
if(temp==10'd0) temp<=10'd999; else temp<=temp-1'b1; end end endmodule
module test_sx_002(CLOCK_50,HEX0,HEX2,HEX1,SW);//采用bcd码 input CLOCK_50; input[1:0] SW;
output[6:0] HEX0,HEX1,HEX2; reg[11:0] temp;
div_clock_1hz c1(CLOCK_50,clock_1,SW[0]); de_16to7seg d1(temp[11:8],HEX2); de_16to7seg d2(temp[7:4],HEX1); de_16to7seg d3(temp[3:0],HEX0);
always@(posedge clock_1 or posedge SW[0]) begin
if(SW[0]) temp<=12'b0; else if(SW[1])
begin //tag 1_top if(temp[3:0]==4'd9) begin temp[3:0]<=4'b0; if(temp[7:4]==4'd9) begin
temp[7:4]<=4'b0; if(temp[11:8]==4'd9) begin
temp[11:8]<=4'b0; end
else temp[11:8]<=temp[11:8]+1'b1; end
else temp[7:4]<=temp[7:4]+1'b1; end
else temp[3:0]<=temp[3:0]+1'b1; end//tag 1_bottom else//SW[1]=0 begin
if(temp[3:0]==4'b0) begin
temp[3:0]<=4'd9; if(temp[7:4]==4'b0) begin
temp[7:4]<=4'd9;