6、Three-level Program Memory Lock 7、256 x 8-bit Internal RAM 8、32 Programmable I/O Lines 9、Three 16-bit Timer/Counters 10、Eight Interrupt Sources
11、Full Duplex UART Serial Channel 12、Low-power Idle and Power-down Modes 13、Interrupt Recovery from Power-down Mode 14、Watchdog Timer 15、Dual Data Pointer 16、Power-off Flag
3 Pin Description
VCC：Supply voltage. GND：Ground.
Port 0：Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs.Port 0 can also be configured to be the multiplexed low-order address /d ata bus during accesses to ext- ernal program and data memory . In this mode, P0 has internal pullups.Port 0 also receives the code by tes during Flash programming and outputs the code bytes during program verification. E x ter nal pullups are required during program verification.
Port 1：Port1 is an 8-bit bidirectional I/O port with internal pullups.The Port 1 output buffers can sink/sourc e four TTL inputs.When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will sourcecurrent (IIL) because of the internal pullups. In addition, P1. 0 and P1.1 can be c onfigured to be the timer/counter 2 external count input (P1. 0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respec tively, as shown in the following table.Port 1 also receives the low-order address bytes during Flash programming and verification.
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Port Pin P1.0 P1.1 P1.5 P1.6 P1.7 Alternate Functions T2 (external count input to Timer/Counter 2), clock-out T2EX (Timer/Counter 2 capture/reload trigger and direction control) MOSI (used for In-System Programming) MISO (used for In-System Programming) SCK (used for In-System Programming) Port2：Port 2 is an 8-bit bidirectional I/O port with internal pullups.The Port 2 output buffers can sink/sourc e four TTL inputs.When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address by te during fetches from ext ernal program memory and during acc esses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, Port 2 uses strong internal pullups when emitting 1s . During acces ses to external data memory that use 8-bit addres ses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.
Port 3：Port 3 is an 8-bit bidirectional I/O port with internal pullups.The Port 3 output buffers can sink/sourc e four TTL inputs.When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will sourcecurrent (IIL) because of the pullups. Port 3 also serves the functions of various special features of the AT89S52, as shown in the following table.Port 3 also receiv es some control signals for Flash programming and verification. Port Pin P3.0 P3.1 P3.2 P3.3 P3.4 P3.5
Alternate Functions RXD(serial input port) TXD(serial output port) INT0(external interrupt 0) INT1(external interrupt 1) T0(timer 0 external input) T1(timer 1 external input) 20
P3.6 P3.7 WR(external data memory write strobe) RD(external data memory read strobe) RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 96 oscillator periods after the Watchdog times out.The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO,the ESET HIGH out feature is enabled.
ALE/PROG：Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clock in g purposes. Note, however, that one ALE pulse is skippedduring eachaccess to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC inst ruction. Otherwise, the pin is weakly pulled high. Setting the ALE -disable bit has no effect if the microcontroller is in external execution mode
PSEN：Program Store Enable (PSEN) is the read strobe to external program memory. When the AT89S52 is executing c ode from external program memory, PSEN is ac tivated twic e eac h machine cycle, except that two PSEN activations are skipped during each access to external data memory.
EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.
XTAL1：Input to the inv erting oscillator amplifier and input to the internal clock operating circuit.
XTAL2：Output from the inverting oscillator amplifier. Table 1. AT89S52 SFR Map and Reset Values
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4 Special Function Registers
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 1.Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip.Read acc es ses to these addresses will in general return random data, and write accesses will have an indeterminate effect.User software should not write 1s to these unlis ted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.
1）Timer 2 Registers: Control and status bits are contained in registers T2CON (shown in Table 2) and T2MOD (shown in Table 3) for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.
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2）Interrupt Registers: The indiv idual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register.
Table 2. T2CON – Timer/Counter 2 Control Register
Symbol TF2 Function Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK = 1 or TCLK = 1. Timer 2 exter nal flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interr upt in up/down counter mode (DCEN = 1). Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. Transmit clock enable. When set, causes the serial por t to use Timer 2 overflow pulses for its transmit clock in serial por t Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial por t. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. Start/Stop control for Timer 2. TR2 = 1 starts the timer. Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for exter nal event counter (falling edge triggered). Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When ei ther RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. EXF2 RCLK TCLK EXEN2 TR2 3）Dual Data Pointer Registers: To facilitate accessing both internal and ex ternal data memory, two bank s of 16-bit Data Pointer Registers are provided: DP0 at SFR address loc ations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1.The user should always initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register.
Table 3a. AUXR: Auxiliary Register
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