Figure6 shows Timer 2 automatically counting up when DCEN=0. In this mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon ov erflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture Mode RCAP2H and RCAP2L are preset by software. If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at ex ternal input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled.
Setting the DCEN bit enables Timer 2 to count up or down,as s hown in Figure 6. In this mode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2 count up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit v alue in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively.
A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers.
The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt.
Figure 6. Timer 2 Auto Reload Mode (DCEN = 0)
Table 4. T2MOD – Timer 2 Mode Control Register
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Symbol — T2OE DCEN Function Not implemented, reserved for future Timer 2 Output Enable bit When set, this bit allows Timer 2 to be configured as an up/down counter Figure7. Timer 2 Auto Reload Mode (DCEN = 1)
Figure 8. Timer 2 in Baud Rate Generator Mode
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9.3 Baud Rate Generator
Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Table 2). Note that the baud rates for transmit and receive can be different if Timer2 is used for the receiver or transmitter and Timer1 is used for the other f unction. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode, as shown in Figure 8.
The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software.The baud rates in Modes 1 and 3 are determined by Timer 2‘s overflow rate according to the following equation.
The Timer can be configured for either timer or counter operation. In most applications, it is configured for timer operation (CP/T2 = 0). The timer operation is different for Timer 2 when it is used as a baud rate generator. Normally, as a timer, it increments every machine cycle (at 1/12 the oscillator frequency). As a baud rate generator, however, it inc rements every state time (at 1/2 the oscillator frequency). The baud rate formula is given below.
Timer 2 as a baud rate generator is shown in Figure 8. This figure is valid only if RCLK or TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not generate an interrupt. Note too, that if EXEN2 is s et, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus, when Timer 2 is in use as a baud rate generator, T2EX can be used as an extra external interrupt.
Note that when Timer 2 is running(TR2 = 1) as a timer in the baud rate generator mode, TH2 or TL2s hould not be read from or written to.Under these conditions, the Timer is incremented every state time, and the results of a read or write may not be accurate.The RCAP2 registers may be read but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timers hould be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers.
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10 Programmable Clock Out
A 50% duty cycle clock can be programmed to come out on P1.0, as shown in Figure 9. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed to input the external clock for Timer/Counter 2 or to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz at a 16 MHz operating frequency.
To configure the Timer/Counter 2 as a clock generator, bit C/T2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and stops the timer.
The clock-out frequency depends on the oscillat or frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L).
In the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This behavior is similar to when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simulta-neously. Note, however, that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L Figure 9. Timer 2 in Clock-Out Mode
11 Interrupts
The AT89S52 has a total of six interrupt vectors: two external interrupts (INT0
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and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Figure 10.
Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once.
Note that Table 5 shows that bit position IE.6 is unimple-mented. In the AT89S52, bit position IE.5 is also unimple-mented. User software should not write 1s to t hes e bit positions, since they may be used in future AT89 products.
Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in regis ter T2CON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact , the service routine may have to dete rmine whether it was TF2 or EXF2 that generated the interrupt,and that bit will hav e to be cleared in software.
The Timer 0 and Timer 1 flags, TF0 and TF1, are s et at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.
Table 5. Interrupt Enable (IE) Register EA - ET2 ES ET1 EX1 ET0 EX0
Figure 10. Interrupt Sources
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