AUXR Address=8EH Reset Value=XXX00XX0B Not Bit Addressable - 7 - 6 - 5 WDIDLE 4 DISRTO - 2 - 1 DISALE 0 3 - Reserved for future expansion DISALE Disable/Enable ALE DISALE Operating Mode 0 ALE is emitted at a constant rate of 1/6 the oscillator frequency 1 ALE is active only during a MOVX or MOVC instruction DISRTO Disable/Enable Reset out DISRTO 0 Reset pin is driven High after WDT times out 1 Reset pin is input only WDIDLE Disable/Enable WDT in IDLE mode WDIDLE 0 WDT continues to count in IDLE mode 1 WDT halts counting in IDLE mode 4）Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to ―1‖ during power up. It can be set and rest under software control and is not affected by reset.
5 Memory Organization
MCS-51 devices have a separate address s pace for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.
1）Program Memory： If the EA pin is connected to GND, all program fetches are directed to external memory.On t he A T89S52, if EA is con nected to VCC, program fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to external memory.
2）Data Memory：The AT89S52 implements 256 by tes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space.When an ins truction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the
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CPU ac ces ses the upper 128 bytes of RAM or the SFR space. Instructions which use direc t addressing access of the SFR space.
For example, the following direc t address ing ins truc tion accesses the SFR at location 0A0H (which is P2).
MOV 0A0H, #data
Instructions that use indirect addressing access the upper 128 byt es of RAM. For example, t he following indirec t addressing instruction, where R0 contains 0A0H, accesses the data by teat addres s 0A0H, rather than P2 (whose address is 0A0H).
MOV @R0, #data
Note that stack operations are examples of in direc t addressing, so the upper 128 bytes of data RAM are available as stack space.
6 Watchdog Timer (One-time Enabled with Reset-out)
The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT c onsists of a 13-bit counter and the Watc- hdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is unning. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware res et or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin. 6.1 Using the WDT
To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H).When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 13-bit counter overflows when it reaches 8191 (1FFFH), and this will reset the device. When the WDT is enabled, it will inc rement every machine c ycle while the osc illator is running. This means the us er must reset the WDT at least every 8191 machinec ycles. To reset the WDT the user must write 01EH and 0E1H to
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WDTRST.WDTRST is a write-only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse duration is 96xTOSC, where TOSC=1/FOSC. To make the best use of the WDT, it s hould be serv iced in those sections of code that will periodically be executed within the time required to prevent a WDT reset. 6.2 WDT During Power-down and Idle
In Power-down mode the oscillator stops, which means the WDT also s tops. While in Power-down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occ ur as it normally does whenever the AT89S52 is reset . Ex iting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the int errupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until theinterrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode.
To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to reset the WDT just before entering Power-down mode.
Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled. The WDT keeps c ounting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S52 while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode.With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.
7 UART
The UART in the AT89S52 operates the same way as the UART in the AT89C51 and AT89C52. For further information on the UART operation, refer to the ATMEL
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Website (http://www.atmel.com). From the home page, select ?Products‘, then ?8051-Architecture Flash Microcontroller‘, then ?Product Overview‘.
8 Timer 0 and 1
Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52. For further information on the timers‘ operation, refer to the ATMEL Web site (http://www.atmel.com). From the home page, s elec t ?Product s‘, then ?8051-Arc hit ecture Flash Microcontroller‘, then ?Product Overview‘.
9 Timer 2
Timer2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table2).Timer2 has three operating modes: capture, auto-reload (upor down c ounting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 3.Timer 2 cons ists of two 8-bit registers, TH2 and TL2. In the Timer func tion, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscilla tor periods , the count rate is 1/12 of the oscillator frequency. Table 3. Timer 2 Operating Modes RCLK+TCLK 0 0 1 × CP/RL2 0 1 × × TR2 1 1 1 0 MODE 16-bit Auto-reload 16-bit Capture Baud Rate Generator （Off） In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of ev ery machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the
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transition was detected. Since two machine cycles (24oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle. 9.1 Capture Mode
In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON.This bit can then be used to generate an interrupt . I f EXEN2 = 1, Timer 2 performs the same operation, but a 1-to-0 trans ition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respec tively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit,like TF2, can generate an interrupt. The capture mode is illustrated in Figure 5.
Figure 5. Timer in Capture Mode
9.2 Auto-reload (Up or Down Counter)
Timer2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see Table 4). Upon reset, the DCEN bit is set to 0 s o that timer2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin.
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