10. Generate the top-level HDL for the FPGA co-processor as shown below.
Figure 12 -- Generating the Top-Level HDL component for the FPGA Co-Processor The Xilinx Multiple Subsystem Generator block wires two or more System Generator designs into a single top-level HDL component that incorporates multiple clock domains. This top-level component includes the logic associated with each System Generator design and additional logic to allow the designs to communicate with one another.
This completes experiment 1.
The FPGA co-processor is now complete, consisting of VLYNQ and SAD modules elaborated as netlists, stitched together in a top-level HDL component named ‘sad_fpga_coprocessor’. It is now ready for integration it into a larger system that contains the entire FPGA infrastructure for the Avnet Spartan-3A DSP DaVinci development Kit.