entity gate_sel is
port(se1: in std_logic; se10: in std_logic; se100: in std_logic; f1: in std_logic; f10: in std_logic; f100: in std_logic; fref: out std_logic; dp1: out std_logic; dp2: out std_logic; dp3: out std_logic); end gate_sel;
architecture Behavioral of gate_sel is
signal sel: std_logic_vector(2 downto 0):=\begin
sel<=se1 & se10 & se100; process(sel,f1,f10,f100) begin case sel is when \ fref<=f1; dp1<='0'; dp2<='1'; dp3<='1'; when \ fref<=f10; dp1<='1'; dp2<='0'; dp3<='1'; when \
fref<=f100; dp1<='1'; dp2<='1'; dp3<='0'; when others => fref<='0'; dp1<='1'; dp2<='1'; dp3<='1'; end case; end process;
end Behavioral;
3、门控电路
entity gate_con is
port(Bsignal: in std_logic;
gate,reset,latch: out std_logic); end gate_con;
architecture Behavioral of gate_con is signal gate_tmp: std_logic:='0'; signal latch_tmp: std_logic:='0';
begin
process(Bsignal) begin
if rising_edge(Bsignal) then gate_tmp<= not gate_tmp; end if;
if falling_edge(Bsignal) then latch_tmp<= not gate_tmp; end if; end process;
gate<=gate_tmp; latch<=latch_tmp;
reset<=(not Bsignal)and(not gate_tmp)and(latch_tmp);
end Behavioral;
4、计数器
entity conunter is
port(count_en: in std_logic; Csignal: in std_logic; clear: in std_logic;
carry_out:out std_logic;
result: out std_logic_vector(3 downto 0)); end conunter;
architecture Behavioral of conunter is
signal count: std_logic_vector(3 downto 0):=\ signal co_tmp: std_logic:='0'; begin
process(count_en,Csignal,clear) begin if clear='1' then count<=\ else if rising_edge(Csignal) then if count_en='1' then if count=\ count<=\ else count<=count+1; end if; end if; end if;
end if; end process;
process(count,clear) begin if clear='1' then co_tmp<='0'; else if count=\ count_en='1' then co_tmp<='1'; else co_tmp<='0'; end if; end if; end process;
carry_out<=co_tmp; result<=count;
end Behavioral;
5、锁存器
entity latch is
port(latchin: in std_logic; overin: in std_logic;
numin1: in std_logic_vector(3 downto 0);
numin2: in std_logic_vector(3 downto 0); numin3: in std_logic_vector(3 downto 0); numin4: in std_logic_vector(3 downto 0); numin5: in std_logic_vector(3 downto 0); numin6: in std_logic_vector(3 downto 0); overout: out std_logic;
numout1: out std_logic_vector(3 downto 0); numout2: out std_logic_vector(3 downto 0); numout3: out std_logic_vector(3 downto 0); numout4: out std_logic_vector(3 downto 0); numout5: out std_logic_vector(3 downto 0); numout6: out std_logic_vector(3 downto 0)); end latch;
architecture Behavioral of latch is
begin
process(latchin,overin,numin1,numin2,numin3,numin4,numin5,numin6) begin
if rising_edge(latchin) then numout1<=numin1; numout2<=numin2; numout3<=numin3; numout4<=numin4; numout5<=numin5; numout6<=numin6; overout<=overin; end if; end process;
end Behavioral;
6、显示控制