5、锁存器
process begin latchin<='0'; wait for 400 ps; latchin<='1'; wait for 100 ps; end process;
process begin overin<='0'; wait; end process;
process begin numin1<=\ wait for 10 ps; numin1<=\ wait for 10 ps; end process;
process begin numin2<=\ wait for 20 ps; numin2<=\ wait for 20 ps; end process;
process begin numin3<=\ wait for 30 ps; numin3<=\ wait for 30 ps; end process;
process begin numin4<=\ wait for 40 ps; numin4<=\ wait for 40 ps; end process;
process begin numin5<=\ wait for 50 ps; numin5<=\ wait for 50 ps; end process;
process begin numin6<=\ wait for 60 ps; numin6<=\ wait for 60 ps; end process;
6、显示部分
process begin f1khz <='1'; wait for 10 ps; f1khz <='0'; wait for 10 ps; end process;
process begin q_over <='0'; wait; end process;
process begin freq_value0 <=\ freq_value1 <=\ freq_value2 <=\ freq_value3 <=\ freq_value4 <=\ freq_value5 <=\
wait; end process;
process begin dp1<='0'; dp2<='1'; dp3<='1'; wait; end process;
7、系统仿真
process begin clk <= '1'; wait for 10 ps; clk <= '0'; wait for 10 ps; end process;
process begin sel1 <= '1'; sel10 <= '0';
sel100 <= '0'; wait; end process;
process begin sig_in <= '1'; wait for 100 us; sig_in <= '0'; wait for 100 us; end process;
七、 结束语
故障：
数码管显示的示数是实际值的一半
问题症结：分频器计数信号值范围小了。 解决办法：放大范围。
感想：
通过此次实验，了解了基于FPGA的数字频率计设计，学会了简单的HDL代码编写，对以后的学习很有帮助。