entity present_con is port(f1khz: in std_logic; q_over: in std_logic;
freq_value0: in std_logic_vector(3 downto 0); freq_value1: in std_logic_vector(3 downto 0); freq_value2: in std_logic_vector(3 downto 0); freq_value3: in std_logic_vector(3 downto 0); freq_value4: in std_logic_vector(3 downto 0); freq_value5: in std_logic_vector(3 downto 0); dp1: in std_logic; dp2: in std_logic; dp3: in std_logic; G: out std_logic;
ledout: out std_logic_vector(6 downto 0); sel: out std_logic_vector(2 downto 0); dp: out std_logic); end present_con;
architecture Behavioral of present_con is
signal switch: std_logic_vector(2 downto 0):=\
signal value_tmp: std_logic_vector(3 downto 0):=\signal led: std_logic_vector(6 downto 0):=\signal dp_tmp: std_logic_vector(2 downto 0):=\signal hide: std_logic_vector(5 downto 0):=\begin
-- clk --
process(f1khz) begin if rising_edge(f1khz) then if switch=\ switch<=\ else switch<=switch+1; end if; end if; end process;
-- show preparation --
process(switch,freq_value0,freq_value1,freq_value2,freq_value3,freq_value4,freq_value5) begin case switch is when \ when \ when \ when \ when \ when \ when others => value_tmp <= \ end case; end process;
process(value_tmp) begin case value_tmp is when \ when \ when \ when \ when \ when \ when \ when \ when \ when \ when others => led <= \ end case;
end process;
dp_tmp<=dp1 & dp2 & dp3;
-- hide vector --
process(dp_tmp,freq_value5,freq_value4,freq_value3,freq_value2) begin case dp_tmp is when \ if freq_value5=\ if freq_value4=\ hide<=\ else hide<=\ end if; else hide<=\ end if; when \ if freq_value5=\ if freq_value4=\ if freq_value3=\ hide<=\ else hide<=\ end if; else hide<=\ end if; else hide<=\ end if; when \ if freq_value5=\ if freq_value4=\ if freq_value3=\ if freq_value2=\ hide<=\ else hide<=\ end if; else
hide<=\ end if; else hide<=\ end if; else hide<=\ end if; when others => hide<=\ end case; end process;
-- show --
process(switch,dp_tmp,led,hide,q_over) begin if q_over='1' then case switch is when \ ledout<=\ dp<='1'; when \ ledout<=\ dp<='1'; when \ ledout<=\ dp<='1'; when \ ledout<=\ dp<='1'; when \ ledout<=\ dp<='1'; when \ ledout<=\ dp<='1'; when others =>
ledout<=\ dp<='1'; end case; else case switch is when \ if hide(0)='1' then ledout<=\ dp<='1'; else ledout<=led; dp<='1'; end if; when \ if hide(1)='1' then ledout<=\ dp<='1'; else ledout<=led; if dp_tmp=\ dp<='0'; else dp<='1'; end if; end if; when \ if hide(2)='1' then ledout<=\ dp<='1'; else ledout<=led; if dp_tmp=\ dp<='0'; else dp<='1'; end if; end if; when \ if hide(3)='1' then ledout<=\ dp<='1';