ElectricalcharacteristicsSTM32FEBKxxInput/outputACcharacteristics
Thedefinitionandvaluesofinput/outputACcharacteristicsaregiveninFigure16andTable31,respectively.Unlessotherwisespecified,theparametersgiveninTable31arederivedfromtestsperformedunderambienttemperatureandVDDsupplyvoltageconditionssummarizedinTable7.Table31.I/Omode(1)
I/OACcharacteristics(1)
Symbolfmax(IO)o
utParameterMaximumfrequency(2)
Outputhightolowlevelfalltime(3)Outputlowtohighlevelrisetime(3)Maximum
frequency(2)Outputhightolowlevelfalltime(3)Outputlowtohighlevelrisetime(3)Maximumfrequency(2)
ConditionsCL=50pF,VDD=2Vto3.6VMin
Max2125UnitMHz10tf(IO)outtr(IO)outfmax(IO)o
utCL=50pF,VDD=2Vto3.6Vns125CL=50pF,VDD=2Vto3.6V1025MHz01tf(IO)outtr(IO)out
CL=50pF,VDD=2Vto3.6Vns25CL=30pF,VDD=2.7Vto3.6VCL=50pF,VDD=2.7Vto3.6VCL=50pF,VDD=2Vto2.7V5030205812581210MHzMHzMHzFmax(IO)o
ut
11tf(IO)out
Outputhightolowlevelfalltime(3)
CL=30pF,VDD=2.7Vto3.6VCL=50pF,VDD=2.7Vto3.6VCL=50pF,VDD=2Vto2.7Vtr(IO)out
Outputlowtohighlevelrisetime(3)
CL=30pF,VDD=2.7Vto3.6VCL=50pF,VDD=2.7Vto3.6VCL=50pF,VDD=2Vto2.7Vns-tEXTIpw
PulsewidthofexternalsignalsdetectedbytheEXTIcontroller
ns1.RefertotheReferenceusermanualUM0306foradescriptionofGPIOPortconfigurationregister.2.ThemaximumfrequencyisdefinedinFigure16.
3.Valuesbasedondesignsimulationandvalidatedonsilicon,nottestedinproduction.
46/67https://houcheng-power.taobao.comwww.st.comSTM32FEBKxxFigure16.I/OACcharacteristicsdefinitionElectricalcharacteristics90P%EXTERNALOUTPUTON50pFtr(IO)out10P?%tr(IO)outTMaximumfrequencyisachievedif(tr+tf)￡2/3)Tandifthedutycycleis(45-55%)whenloadedby50pFai141315.3.13NRSTpincharacteristics
TheNRSTpininputdriverusesCMOStechnology.Itisconnectedtoapermanentpull-upresistor,RPU(seeTable29).Unlessotherwisespecified,theparametersgiveninTable32arederivedfromtestsperformedunderambienttemperatureandVDDsupplyvoltageconditionssummarizedinTable7.Table32.SymbolVIL(NRST)VIH(NRST)Vhys(NRST)RPUVF(NRST)VNF(NRST)
NRSTpincharacteristics(1)
ParameterNRSTInputlowlevelvoltageNRSTInputhighlevelvoltageNRSTSchmittvoltagehysteresistriggerVIN=VSS30ConditionsMin–0.522004050100300k?nsμsTypMax0.8VDD+0.5UnitVWeakpull-upequivalentresistor(2)NRSTInputfilteredpulse(3)NRSTInputnotfilteredpulse(3)
1.TBDstandsfortobedetermined.
2.Thepull-upisdesignedwithatrueresistanceinserieswithaswitchablePMOS.ThisPMOScontribution
totheseriesresistancemustbeminimum(~10%order).3.Valuesguaranteedbydesign,nottestedinproduction.
47/67https://houcheng-power.taobao.comwww.st.comElectricalcharacteristicsFigure17.RecommendedNRSTpinpr。tecti。nVDDNRST0.1μFRPUFILTERInternalResetSTM32FEBKxxExternalresetcircuitSTM32F101xxai14132b1.Theresetnetworkprotectsthedeviceagainstparasiticresets.
2.TheusermustensurethatthelevelontheNRSTpincangobelowtheVIL(NRST)maxlevelspecifiedin
Table32.Otherwisetheresetwillnotbetakenintoaccountbythedevice.
5.3.14TIMtimercharacteristics
Unlessotherwisespecified,theparametersgiveninTable33arederivedfromtestsperformedunderambienttemperature,fPCLKxfrequencyandVDDsupplyvoltageconditionssummarizedinTable7.RefertoSection5.3.12:I/Oportpincharacteristicsfordetailsontheinput/outputalternatefunctioncharacteristics(outputcompare,inputcapture,externalclock,PWMoutput).Table33.Symboltres(TIM)
TIMx(1)characteristicsParameterTimerresolutiontimeTimerexternalclockfrequencyonCH1toCH4Timerresolution16-bitcounterclockperiodwheninternalclockisselectedMaximumcountpossiblefTIMxCLK=72MHz1fTIMxCLK=72MHz0.0139ConditionsMin1fTIMxCLK=72MHz13.90fTIMxCLK=72MHz0fTIMxCLK/236166553691065536×6553659.6MaxUnittTIMxCLKnsMHzMHzbittTIMxCLKμstTIMxCLKsfEXTResTIMtCOUNTER
tMAX_COUNT
?
TIMxisusedasageneraltermtorefertotheTIM1,TIM2,TIM3andTIM4timers.
https://houcheng-power.taobao.com48/67www.st.comSTM32FEBKxxElectricalcharacteristics5.3.15Communicationsinterfaces
I2Cinterfacecharacteristics
Unlessotherwisespecified,theparametersgiveninTable34arederivedfromtestsperformedunderambienttemperature,fPCLK1frequencyandVDDsupplyvoltageconditionssummarizedinTable7.2
TheSTM32FEBKxxperformancelineICinterfacemeetstherequirementsofthestandard2
ICcommunicationprotocolwiththefollowingrestrictions:theI/OpinsSDAandSCLaremappedtoarenot“true”open-drain.Whenconfiguredasopen-drain,thePMOSconnectedbetweentheI/OpinandVDDisdisabled,butisstillpresent.Inaddition,thereisaprotectiondiodebetweentheI/OpinandVDD.Asaconsequence,whenmultiplemasterdevicesare22
connectedtotheICbus,itisnotpossibletopowerofftheSTM32FEBKxxwhileanotherICmasternoderemainspoweredon.Otherwise,theSTM32FEBKxxwouldbepoweredbytheprotectiondiode.TheICcharacteristicsaredescribedinTable34.ReferalsotoSection5.3.12:I/Oportpincharacteristicsformoredetailsontheinput/outputalternatefunctioncharacteristics(SDAandSCL).Table34.I2CcharacteristicsStandardI2C(1)Min4.74.02500(3)
10003004.04.74.04.7400modeMaxFastmodeI2C(1)(2)Min1.30.61000(4)
20+0.1Cb20+0.1Cb0.60.60.61.3400μsμsμspF900(3)300nsSDAandSCLfalltimeStartconditionholdtimeRepeatedStartconditionsetuptimeStopconditionsetuptimeStoptoStartconditiontime(busfree)Capacitiveloadforeachbusline300μsMaxUnit2
Symboltw(SCLL)tw(SCLH)tsu(SDA)th(SDA)tr(SDA)tr(SCL)tf(SDA)tf(SCL)th(STA)tsu(STA)tsu(STO)tw(STO:STA)Cb
ParameterSCLclocklowtimeSCLclockhightimeSDAsetuptimeSDAdataholdtimeSDAandSCLrisetime1.ValuesbasedonstandardI2Cprotocolrequirement,nottestedinproduction.
2.fPCLK1mustbehigherthan2MHztoachievethemaximumstandardmodeI2Cfrequency.Itmustbehigherthan4MHztoachievethemaximumfastmodeI2Cfrequency.3.ThemaximumholdtimeoftheStartconditionhasonlytobemetiftheinterfacedoesnotstretchthelowperiodofSCLsignal.4.Thedevicemustinternallyprovideaholdtimeofatleast300nsfortheSDAsignalinordertobridgetheundefinedregionofthefallingedgeofSCL.
https://houcheng-power.taobao.comwww.st.com49/67ElectricalcharacteristicsFigure18.I2CbusACwaveformsandmeasurementcircuitVDD4.7k?I2CbusVDD4.7k?STM32FEBKxxSDASCLSTM32FEBKxx100?100?STARTREPEATEDSTARTtsu(STA)SDAtf(SDA)th(STA)SCLtw(SCKH)tr(SCK)tf(SCK)tsu(STO)ai14149bSTARTtr(SDA)tw(SCKL)tsu(SDA)th(SDA)STOPtsu(STA:STO)1.MeasurementpointsaredoneatCMOSlevels:0.3VDDand0.7VDD.
Table35.SCLfrequency(fPCLK1=36MHz.,VDD=3.3V)(1)(2)(3)
I2C_CCRvaluefSCL(kHz)RP=4.7k?4003002001005020TBDTBDTBDTBDTBDTBD1.TBD=tobedetermined.
2.RP=Externalpull-upresistance,fSCL=I2Cspeed,
3.Forspeedsaround200kHz,thetoleranceontheachievedspeedisof±5%.Forotherspeedranges,the
toleranceontheachievedspeed±2%.Thesevariationsdependontheaccuracyoftheexternalcomponentsusedtodesigntheapplication.
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