end if; end if; end process; END fun;
18、看下面原理图，写出相应VHDL描述
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY MYCIR IS PORT (A, CLK : IN STD_LOGIC; C, B : OUT STD_LOGIC ); END MYCIR;
ARCHITECTURE BEHAV OF MYCIR IS SIGNAL TA : STD_LOGIC; BEGIN PROCESS (A, CLK) BEGIN IF CLK’EVENT AND CLK = ‘1’ THEN TA <= A; B <= TA; C <= A AND TA; END IF; END PROCESS; END BEHAV;
19、根据原理图写出相应的VHDL程序：
Library ieee;
Use ieee.std_logic_1164.all; Entity mycir is Port ( din, clk : in std_logic; Qout : out std_logic); End mycir;
Architecture behave of mycir is Signal a, b, c; Begin Qout <= c nand (a xor b); Process (clk) Begin If clk’event and clk = ‘1’ then A <= din; B <= A; C <= B; End if; End process; End behave;
20、根据原理图写出相应的VHDL程序：
Library ieee;
Use ieee.std_logic_1164.all; Entity mycir is Port ( A, B, clk : in std_logic; Qout : out std_logic); End mycir;
Architecture behave of mycir is Signal ta, tb, tc; Begin tc <= ta nand tb; Process (clk) Begin If clk’event and clk = ‘1’ then Ta <= A; Tb <= B; End if; End process; Process (clk, tc)
Begin If clk = ‘1’ then Qout <= c; End if; End process; End behave;