PORT (A1,B1: IN std_logic;
C1: OUT std_logic); END COMPONENT; SIGNAL X,Y: std_logic ;
BEGIN
U1:yf2 PORT MAP (A,B,X); U2:yf2 PORT MAP (C,D,Y);
U3:yf2 PORT MAP (A1 => X, C1=>Z, B1 => Y); END a;
11、用VHDL语言编写半加器和或门器件的程序，如图所示：
半加器程序： library ieee;
use ieee.std_logic_1164.all; entity h_adder is port(a,b:in std_logic; co,so:out std_logic); end h_adder;
architecture one of h_adder is begin
so<=not(a xor(not b)); co<=a and b; end one; 或门程序： library ieee;
use ieee.std_logic_1164.all; entity or2a is
port(a,b:in std_logic; c:out std_logic); end or2a;
architecture one of or2a is begin c<=a or b; end one;
12、在上道题目的基础上用元件例化语句设计1位全加器。
主程序： library ieee;
use ieee.std_logic_1164.all; entity f_adder is
port(ain,bin,cin:in std_logic; cout,sum:out std_logic); end entity f_adder;
architecture fd1 of f_adder is component h_adder port(a,b:in std_logic;
co,so:out std_logic); end component; component or2a
port(a,b:in std_logic; c:out std_logic); end component; signal d,e,f:std_logic; begin
u1 : h_adder port map(a=>ain,b=>bin,co=>d,so=>e); u2 : h_adder port map(a=>e,b=>cin,co=>f,so=>sum); u3 : or2a port map(d,f,cout); end fd1;
13、试用VHDL语言编写一个七段共阴极LED管译码器程序 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY sevenLED IS
PORT(D : IN INTEGER RANGE 0 TO 9;
S : OUT STD_LOGIC_VECTOR(0 DOWNTO 6) ); END sevenLED ;
ARCHITECTURE a OF sevenBCD IS BEGIN
PROCESS(D) BEGIN
CASE D IS
WHEN 0 => S<=\ --0 WHEN 1 => S<=\ --1 WHEN 2 => S<=\ --2 WHEN 3 => S<=\ --3 WHEN 4 => S<=\ --4 WHEN 5 => S<=\ --5 WHEN 6 => S<=\ --6 WHEN 7 => S<=\ --7 WHEN 8 => S<=\ --8 WHEN 9 => S<=\ --9
WHEN OTHERS => S<=\ END CASE;
END PROCESS; END a;
14、试用VHDL语言编写八选一数据选择器程序 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY multi_8v IS
PORT(S : IN STD_LOGIC_VECTOR (2 DOWNTO 0); A,B,C,D,E,F,G,H : IN STD_LOGIC; Y : OUT STD_LOGIC );
END multi_8v;
ARCHITECTURE a OF multi_8v IS BEGIN PROCESS BEGIN
IF (S=\ Y <= A;
ELSIF (S=\ Y <= B;
ELSIF (S=\ Y <= C;
ELSIF (S=\ Y <= D;
ELSIF (S=\ Y <= E;
ELSIF (S=\ Y <= F;
ELSIF (S=\ Y <= G;
ELSIF (S=\
Y <= H; END IF;
END PROCESS; END a;
15、试编写一个完整VHDL程序，实现下图所示电路的功能；
CABOUTPUT
LIBRARY IEEEE；
USE IEEE.STD_LOGIC_1164.ALL; ENTITY TI5 IS
PORT(A,B,C: IN STD_LOGIC;
OUTPUT: OUT STD_LOGIC); END TI5;
ARCHITECTURE ART OF TI5 IS BEGIN
OUTPUT<=(A NAND B) NAND ((NOT A ) NAND C ); END ART;
16、试用VHDL编写程序实现七段显示译码器。（数码管为共阴极）
a
f b
g
e c
d
Library ieee;
Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Entity btod is
Port(A : in std_logic_vector(3 downto 0); Y : out std_logic_vector(6 downto 0)); End btod;
Architecture a1 of btod is Begin Process(d) Begin Case A is
when \--0 when \--1
when \--2 when \--3 when \--4 when \--5 when \--6 when \--7 when “1000“ => Y<= “1111111 ”; --8 when “1001“ => Y<= \--9 End case; End process; End a1;
17、试用VHDL编写程序实现二十四进计数器；
LIBRARY ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; ENTITY CNT24 IS
PORT(clk,reset : IN STD_LOGIC;
STD_LOGIC;
enhour : OUT END entity CNT24;
ARCHITECTURE fun OF CNT24 IS
SIGNAL count: STD_LOGIC_VECTOR( 6 downto 0); BEGIN
daout <= count;
daout: out std_logic_vector (6 downto 0));
process ( clk,reset,sethour) begin
if (reset='0') then
count <= \
elsif (clk' event and clk='1') then
if (count(3 downto 0)=\ if (count <16#24#) then
if (count=\
enhour<='1'; count<=\
ELSE
count<=count+7; end if;
else count<=\
end if;
elsif(count <16#24#) then count <= count + 1; enhour<='0' after 100 ns; else
count<=\