WHEN OTHERS =>Y<=\
END CASE;
ELSE
Y<=\
END IF;
END PROCESS encoder; END fun;
3、编写包含以下内容的实体代码 端口 D 为12位输入总线 端口 OE 和 CLK 都是1位输入 端口 AD 为 12位双向总线 端口 A为12位输出总线 端口 INT 是1位输出 端口 AS 是一位输出同时被用作内部反馈 LIBRARY ieee;
USE ieee.std_logic_1164.ALL; ENTITY my_design IS PORT (
d: IN std_logic_vector(11 DOWNTO 0); oe, clk: IN std_logic;
ad: INOUT std_logic_vector(11 DOWNTO 0); a: OUT std_logic_vector(11 DOWNTO 0); int: OUT std_logic; as: BUFFER std_logic); END my_design;
4、利用MAX+PLUSⅡ库中元器件D触发器（图形符号见图1）和与元件例化，完成如下图所示的电路设计。
LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY shifter IS
PORT( din,clk: IN std_logic;
dout: OUT std_logic); END shifter;
ARCHITECTURE a OF shifter IS
my_desi COMPONENT dff
PORT (D，clk: IN std_logic;
Q: OUT std_logic); END COMPONENT;
SIGNAL d: std_logic _vector (4 DOWNTO 0); BEGIN
d(0)<=din;
U0:dff PORT MAP (d(0),clk,d(1)); U1:dff PORT MAP (d(1),clk,d(2));
U2:dff PORT MAP (D=>d(2), clk=> clk, Q =>d(3)); U3:dff PORT MAP (D=>d(3), clk=> clk, Q =>d(4)); dout<=d(4); END a;
5、已知电路原理图如下，请用VHDL语言编写其程序
library ieee;
use ieee.std_logic_1164.all; ENTITY mux21 is port(a,b,s:in bit; y:out bit); end mux21;
architecture one of mux21 is single d,e:bit; begin
d<=a and (not)s; e<=b and s; y<=d or e; end one;
6、用元件例化语句设计如图所示电路。元件为2输入与非门。
LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY yf4 IS
PORT( A,B,C,D: IN std_logic;
Z: OUT std_logic); END yf4;
ARCHITECTURE a OF yf4 IS COMPONENT yf2
PORT (A1,B1: IN std_logic;
C1: OUT std_logic); END COMPONENT; SIGNAL X,Y: std_logic ;
BEGIN
U1:yf2 PORT MAP (A,B,X); U2:yf2 PORT MAP (C,D,Y);
U3:yf2 PORT MAP (A1 => X, C1=>Z, B1 => Y); END a;
7、已知2-4译码器真值表、原理图符号如下，请编写其程序。
G1 G2AN A1 Y3 Y2 Y2 G2BN A0 Y0 0 x x X X 1 1 1 1 1 X X X 1 1 X 1 X X 1 1 1
1 1 1 1 1 1 0 0 0 0 1 1 1
0 1 0 0 0 1 1 1 0
1 1 0 0 1 0 1 0 1
1 1 0 0 1 1 0 1 1
1 LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY decoder2_4 IS PORT( A1, A0,G1,G2A,G2B: IN STD_LOGIC; Y: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END decoder2_4;
ARCHITECTURE fun OF decoder2_4 IS
SIGNAL indata: STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN
indata <= C&B&A; encoder:
PROCESS (indata, G1, G2A,G2B) BEGIN IF (G1='1' AND G2A='0' AND G2B='0') THEN CASE indata IS WHEN \ WHEN \ WHEN \ WHEN \
WHEN OTHERS =>Y<=\ END CASE; ELSE
Y<=\ END IF;
END PROCESS encoder; END fun;
8、设计一个带有异步清零功能的十进制计数器。计数器时钟clk上升沿有效、清零端CLRN、进位输出co。
library ieee;
use ieee.std_logic_1164.all; entity counter10 is
port(clk,CLRN:in std_logic; dout:out integer range 0 to 9); end counter10;
architecture behav of counter10 IS begin process(clk) variable cnt:integer range 0 to 9; begin
IF CLRN='0'THEN CNT:=0; ELSIF clk='1'and clk'event then if cnt=9 then cnt:=0; else cnt:=cnt+1; end if; end if;
dout<=cnt; end process; end behav;
9、具有清零端的4位二进制计数器如下图所示，请用VHDL语言编写其程序。
程序： library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt4 is
port(clk:in std_logic; clr:in std_logic;
q:buffer std_logic_vector(3 downto 0)); end cnt4;
architecture behav of cnt4 is begin
process(clr,clk) begin
if clr='1' then q<=\
elsif (clk'event and clk='1') then q<=q+1; end if;
end process; end behav;
10、用元件例化语句设计如图所示电路。元件为2输入与非门。
LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY yf4 IS
PORT( A,B,C,D: IN std_logic; Z: OUT std_logic); END yf4;
ARCHITECTURE a OF yf4 IS COMPONENT yf2